基于CPRI协议的FPGA高速数据接口模块设计与实现

发布时间：2018-06-10 17:32

本文选题：IQ数据 + FPGA　；参考：《北京邮电大学》2014年硕士论文

【摘要】：随着科技不断进步,通信技术的不断发展,对通信技术的研究工作持续进行。TD-LTE(Time Division Long Term Evolution)作为我国研发的通信技术标准TD-SCDMA(Time Division-Synchronization Code Division Multiple Access)的长期演进技术,我国在“新一代宽带无线通信网”计划中对TD-LTE研究做出了巨大投入。Ir接口协议是TD-LTE中基站设备和射频设备之间的主要接口协议。深入研究Ir接口协议,对于完善协议功能,推进TD-LTE的推广具有重要意义。本文为验证Ir接口对用户IQ (In-phase Quadrature)数据的处理功能,需要将基站设备中CPRI核解析出的IQ数据,实时高速传输至上位机进行短时存储。根据本项功能需求,本文设计实现IQ数据的高速传输模块。主要的工作包括：采用从上到下,模块化的设计思想对数据传输模块进行整体框架设计；采用改进的异步FIFO对不同时钟频率下的IQ数据实现跨时钟域同步,实现对不同CPRI线速率的自动速率匹配；提出基于FPGA实现数据传输协议栈的方案,分层实现UDP/IP传输协议栈的传输层,网络层和数据链路层协议的数据包封装和向下层发送状态机,实现IQ数据高速实时发送：本文为测试基站设备和射频设备在IQ数据传输过程中的处理能力,需要对发送的IQ数据进行高速缓存,对接收到的IQ数据进行实时比对,比对结果上报上位机。为此,本文设计并实现高速IQ数据缓存模块,主要工作包括：突破传统缓存方式,提出采用FPGA外部DDR3SDRAM和内部BRAM相结合的方法,在PLB总线控制下,实现对IQ数据的高速缓存；利用FPGA内部BRAM缓存实现对不同CPRI线速率条件下的IQ数据自动速率匹配；提出全局输入时钟缓冲和数字时钟管理单元相结合的时钟设计方法,为高速IQ数据缓存模块提供可靠的时钟支持。采用PlanAhead对高速IQ数据缓存模块的布局优化设计。通过测试验证,本文所实现的高速数据接口模块,可实现对IQ数据高速实时传输和高速缓存的功能,满足功能需求指标。
[Abstract]:With the progress of science and technology and the development of communication technology, the research work on communication technology has been carried out continuously. TD-LTEtime Division long term Evolution is the long-term evolution technology of TD-SCDMA-Time Division-Synchronization Code Division multiple access, which is developed in China. China has made a huge investment in the research of TD-LTE in the "New Generation Broadband Wireless Communication Network" project. The ir interface protocol is the main interface protocol between base station equipment and radio frequency equipment in TD-LTE. In order to improve the protocol function and promote the promotion of TD-LTE, it is of great significance to study the ir interface protocol in depth. In order to verify the processing function of ir interface to user IQ / In-phase Quadraturedata, we need to parse the IQ data from CPRI core in base station equipment. Real-time high-speed transmission to the host computer for short-time storage. According to the requirement of this function, this paper designs and implements the high-speed transmission module of IQ data. The main works are as follows: the whole frame of the data transmission module is designed with the idea of top-down and modularization, and the improved asynchronous FIFO is used to synchronize the IQ data at different clock frequencies across the clock domain. To realize the automatic rate matching of different CPRI line rates, the scheme of implementing data transmission protocol stack based on FPGA is proposed, and the transport layer of UDP / IP transmission protocol stack, the packet encapsulation of network layer and data link layer protocol and the sending state machine of data link layer protocol are implemented layer by layer. In order to test the processing ability of base station equipment and radio frequency equipment in the process of IQ data transmission, it is necessary to cache the transmitted IQ data and compare the received IQ data in real time. Compare the results to the upper computer. Therefore, this paper designs and implements the high-speed IQ data cache module. The main work includes: breaking through the traditional buffer mode, a method of combining DDR3 SDRAM with internal BRAM is put forward to realize the cache of IQ data under the control of PLB bus; Automatic rate matching of IQ data under different CPRI line rates is realized by using internal Bram buffer in FPGA, and a clock design method combining global input clock buffer and digital clock management unit is proposed. It provides reliable clock support for high speed IQ data cache module. Plan head is used to optimize the layout of high speed IQ data buffer module. The test results show that the high-speed data interface module of this paper can realize the function of high-speed real-time transmission and cache of IQ data, and meet the functional requirements.
【学位授予单位】：北京邮电大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN929.5;TN791

【参考文献】