差分跳频通信系统的研究与FPGA实现

发布时间：2018-06-12 06:34

本文选题：差分跳频 + 现场可编程门阵列　；参考：《大连海事大学》2014年硕士论文

【摘要】：差分跳频技术(Differential Frequency Hopping, DFH)是一种集调制、解调和跳频图案为一体的新型跳频技术。它从高速跳频出发,较好地解决了提高数据速率、抗多径、抗跟踪干扰的问题,由于差分跳频图案是基于有向图的遍历,差分跳频序列还具有一定的纠检错能力,进一步提高了系统性能,这一切都使得差分跳频技术代表了新一代短波抗干扰通信技术的发展方向。另一方面,由于现场可编程门阵列(Field Programmable Gate Array, FPGA)具有较高的灵活性、可重复利用性和开发周期短等优点,在通信系统设计开发中得到了广泛的应用。本文从常规跳频通信系统的基本原理与性能指标出发,重点研究了差分跳频通信系统的关键技术。在此基础上给出了差分跳频通信系统的总体结构和设计参数。整个系统包括了发送和接收两部分。在发送系统中,主要包括信源模块、串并转换模块、频率转移函数模块、DDS模块；在接收系统中,主要包括FFT变换模块、频率序列识别模块、基于Viterbi算法的译码模块、频率转移函数反变换模块、并串转换模块。本文在Xilinx的ISE10.1开发环境下,采用Verilog硬件描述语言各个模块进行了详细设计,采用Synplify Pro9.6.2综合工具对各个模块进行综合,并给出了相应的寄存器传输级(Register-Transfer Layer, RTL)的设计电路图,采用Modelsim6.5a仿真工具对各个模块和系统进行仿真,然后将发送和接收各个模块整合到一起进行了整个系统的仿真。最后将设计好的差分跳频通信系统下载到由Xilinx公司生产的Spartan-3E FPGA硬件平台进行了系统测试。仿真和测试结果表明：各模块和整体系统的软件仿真和硬件测试结果都是正确的,接收端能够正确解调出信源数据,基本满足了对差分跳频通信系统的设计要求。
[Abstract]:Differential Frequency hopping (DFH) is a new frequency hopping technique which integrates modulation, demodulation and frequency hopping pattern. It solves the problem of improving data rate, resisting multipath and anti-tracking interference from high speed frequency hopping. Because differential frequency hopping pattern is based on traversal of directed graph, differential frequency hopping sequence also has the ability of correcting errors. The system performance is further improved, all of which make the differential frequency hopping technology represent the development direction of the new generation of shortwave anti-jamming communication technology. On the other hand, field programmable gate array (FPGA) has the advantages of high flexibility, reusability and short development cycle. It has been widely used in the design and development of communication system. Based on the basic principle and performance index of the conventional frequency-hopping communication system, this paper focuses on the key technologies of the differential frequency-hopping communication system. On this basis, the overall structure and design parameters of the differential frequency hopping communication system are given. The whole system includes two parts: sending and receiving. In the transmission system, it mainly includes the source module, the series-parallel conversion module, the frequency transfer function module and the DDS module; in the receiving system, it mainly includes the FFT transform module, the frequency sequence identification module, the decoding module based on Viterbi algorithm. Frequency transfer function inverse transform module, and serial conversion module. In this paper, in the ISE10.1 development environment of Xilinx, every module of Verilog hardware description language is designed in detail, the Synplify Pro9.6.2 synthesis tool is used to synthesize each module, and the design circuit diagram of register transfer level Register-Transfer layer (RTL) is given. Each module and system are simulated with Modelsim6.5a simulation tool, and the whole system is simulated by integrating the sending and receiving modules together. Finally, the designed differential frequency hopping communication system is downloaded to the Spartan-3E FPGA hardware platform produced by Xilinx for system test. The simulation and test results show that the software simulation and hardware test results of each module and the whole system are correct. The receiver can demodulate the source data correctly, which basically meets the design requirements of the differential frequency hopping communication system.
【学位授予单位】：大连海事大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN914.41

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