快速锁定的CMOS电荷泵锁相环的研究

发布时间：2018-06-17 07:44

本文选题：电荷泵锁相环 + 鉴频鉴相器　；参考：《南京理工大学》2014年硕士论文

【摘要】：锁相环(Phase-Locked Loop, PLL)是一种同步反馈系统,它在很多领域都有着广泛的应用。电荷泵锁相环(Charge Pump PLL,CPPLL)是目前锁相环设计的主流,它具有锁定相差小、高速等优点。首先,本文介绍了CPPLL的工作原理以及它的五个组成模块——鉴频鉴相器(PFD)、电荷泵(CP)、环路滤波器(LPF)、压控振荡器(VCO)和分频器(Divider)的结构和工作原理。其次,将电荷泵锁相环的五个模块的不同结构进行了对比,确定这五个模块在本设计中所采用的结构。接着,基于TSMC0.18um CMOS工艺,运用ADS软件设计了各模块的具体电路。改进的鉴频鉴相器死区很小,约45ps。改进的电荷泵的充、放电流失配很小,介于-0.71%和0.03%之间,电流变化率也很小,约1%。LC压控振荡器的中心频率为2GHz,输出频率范围为1.799GHz到2.567GHz。分频器采用可以快速工作的TSPC-DFF结构5级级联,实现了32分频。系统整体仿真结果显示输出波形占空比接近50%,22us时锁相环基本锁定。最后,采用Spectre工具,在tsmc18rf的模型库下对鉴频鉴相器和分频器这两个子模块进行了仿真,使用Virtuoso工具完成了这两个子模块的版图设计,并利用Calibre提取了它们版图中的寄生参数并进行了后仿真。最后,对鉴频鉴相器和分频器的前仿真结果和后仿真结果进行了对比分析。
[Abstract]:Phase-Locked Loop (PLL) is a synchronous feedback system, which is widely used in many fields. Charge pump PLL (charge pump PLL) is the main design of PLL at present. It has the advantages of small locking phase difference and high speed. Firstly, this paper introduces the working principle of CPPLL and the structure and working principle of its five modules, the frequency discriminator PFDO, the charge pump, the loop filter, the VCO) and the divider Divider. Secondly, the different structures of the five modules of the charge pump PLL are compared, and the structure of the five modules in this design is determined. Then, based on TSMC 0.18um CMOS process, the specific circuits of each module are designed by using ads software. The improved phase discriminator has a very small dead zone of about 45 ps. The discharge loss distribution of the improved charge pump is very small, between -0.71% and 0.03%, and the current change rate is also very small. The central frequency of the voltage controlled oscillator is about 2 GHz, and the output frequency ranges from 1.799 GHz to 2.567 GHz. The frequency divider adopts TSPC-DFF structure 5 stage cascade which can work fast and realizes 32 frequency division. The simulation results show that the phase-locked loop is basically locked when the duty cycle of the output waveform is close to 50 and 22us. Finally, the two sub-modules of frequency discriminator and frequency divider are simulated by using Spectre tool under the tsmc18rf model library, and the layout design of the two sub-modules is completed by using the Virtuoso tool. The parasitic parameters in their layout are extracted by calibre and then simulated. Finally, the pre-simulation and post-simulation results of the phase discriminator and frequency divider are compared and analyzed.
【学位授予单位】：南京理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8

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