基于RRNS纠错算法研究

发布时间：2018-06-23 03:21

本文选题：余数系统 + 数字信号处理　；参考：《电子科技大学》2014年硕士论文

【摘要】：随着现代通信系统、密码系统、图像处理系统、网络处理器系统等复杂度日益增加,并行处理技术结合Very Large Scale Integration (VLSI)技术已成为各领域共同的发展方向。基于VLSI技术的专用Digital Signal Processing (DSP)芯片在完成复杂的信源编码、信道译码、解调、信号变换等高速信号处理中具有不可替代的地位,而处理速度和功耗的矛盾是VLSI设计中面临的重大问题,并行处理技术是有效的解决方式之一。而并行处理的研究方向中,余数系统Residue Number System (RNS)所代表的并行数值表征系统具有算法前端的适应性,进而成为并行处理技术的重要研究方向之一。应用RNS后将大大改善传统并行处理器中的单个处理单元的性能。与传统二进制数值表征系统相比,RNS在算法级的并行性同时也使得其基本运算,如模加法／模乘法,大小比较、符号检测、余数基构建等成为了其实际应用中的关键问题。余数系统余数基组间相互独立的特性,使得余数系统在差错控制方面必然将各个领域产生较大影响,进而推进余数系统的在并行处理技术中的应用。近年来出现的阵列软件无线电技术在多模式通信及高速信号处理中具有重要作用,同时随着集成电路制造工艺进入深亚微米阶段,芯片内噪声所带来的片上误码己成为不可忽略的问题。在信息处理速度以及功耗等控制的研究方向之外,信息的可靠传输、存储也是余数系统的重要研究方向之一。本文围绕基于RRNS的检错和纠错能力等问题,提出一种类比于信道编码中线性系统分组码的信道编码、信道译码设计方法的纠错算法结构。定义了通过基于中国剩余定理Chinese Reminder Theory (CRT)的基扩展Base Extension (BEX)计算方法得到的扩展余数xk+s,s=1,2,…,r完成信道编码的功能,并通过定义特殊校验矩阵HRRNS以完成校正子向量的计算。并通过类比线性分组码中标准阵以及校正子译码的概念,定义了基于RRNS码的检错/纠错结构。在上述RRNS码差错控制结构下,本文对前述RRNS信道编码设计进行改进,进而使得新提出的纠错算法具有良好的"time x area"性能。本文将对比国外主要的三类基于Redundant Residue Number System (RRNS)的单错误纠错算法：1.基于Mixed Radix Conversion (MRC)的基扩展计算方法以及校正子计算,通过一致性方程求解对单个错误进行定位及纠错；2.同本文提出算法中伪校正子计算部分相同,并利用伪校正子中“量值”与单个余数错误的对应关系完成对单个错误的定位及纠错；3.运用MRC方法结合数值缩放技术建立缩放值与错误向量的映射,进而完成单个错误的定位及纠错。本文在提出纠错算法的基本理论基础以及实现结构的同时给出对应的完整的验证(功能仿真、门级仿真、Field Programmable Gate array (FPGA)加速验证)以及Application Specific integrated Circuit (ASIC)设计流程。本文将从延时、资源消耗方面对比本文提出算法以及上述国外主要的三类算法,进而说明本文提出的算法更加适用于VLSI的实现,在本文的综合结果对比分析中将对本文算法的自动化设计、验证、综合平台进行实现,并采用该自动化平台,对动态范围为64位、128位的模数组的RRNS进行对比评估。
[Abstract]:With the modern communication system, the complexity of cryptographic system, image processing system and network processor system is increasing. Parallel processing technology combined with Very Large Scale Integration (VLSI) technology has become a common development direction. The special Digital Signal Processing (DSP) chip based on VLSI technology has completed the complex source coding. Code, channel decoding, demodulation, signal transformation and other high-speed signal processing have an irreplaceable position, and the contradiction between processing speed and power consumption is a major problem in VLSI design. Parallel processing technology is one of the effective solutions. In the research direction of parallel processing, the parallelism represented by the remainder system Residue Number System (RNS) The application of RNS will greatly improve the performance of the single processing unit in the traditional parallel processor. Compared with the traditional binary numerical representation system, the parallelism of RNS at the algorithm level also makes the basic operation, such as the addition of the model. The method / modulus multiplication, size comparison, symbol detection, and the remainder base construction have become the key problems in their practical applications. The independent characteristics of the remainder system remainder base groups make the remainder system have a great influence in the field of error control, and then promote the application of the remainder system in parallel processing technology in recent years. Array software radio plays an important role in multi mode communication and high speed signal processing. At the same time, with the integrated circuit manufacturing technology entering the deep sub micron stage, the on-chip bit error caused by the noise in the chip has become a problem that can not be ignored. The reliable transmission of interest and storage is one of the important research directions of the remainder system. In this paper, a kind of error correction algorithm structure for channel coding and channel decoding is proposed around the channel coding based on the error detection and error correction ability of RRNS, which is based on the Chinese remainder theorem Chinese Remind. Er Theory (CRT) based on extended Base Extension (BEX) algorithm obtains the extended residue xk+s, s=1,2,... R completes the function of channel coding and completes the calculation of the corrected subvectors by defining a special checksum matrix HRRNS. The error detection / error correction structure based on the RRNS code is defined by the concept of the standard array and the correction subcode in the analogical linear block code. Under the aforementioned RRNS code error control structure, the previous RRNS channel coding is designed in this paper. In this way, the proposed error correction algorithm has a good "time x area" performance. This paper compares the three major single error correction algorithms based on Redundant Residue Number System (RRNS) in foreign countries: 1. based on Mixed Radix Conversion (MRC) base extension calculation method and correction subcalculation, through the consistency equation solution Location and error correction for a single error; 2. the location and error correction of a single error are completed by the corresponding relationship between the pseudo corrector and the error of a single remainder in the pseudo corrector. 3. the mapping of the scaling value and the error vector by the MRC method combined with the numerical scaling technique is used. Complete the basic theoretical basis of the error correction algorithm and the implementation of the structure, this paper gives the corresponding complete verification (functional simulation, gate level simulation, Field Programmable Gate array (FPGA) acceleration verification) and Application Specific integrated Circuit (ASIC) design process. This article will be from extension In the aspect of resource consumption, the algorithm and the three main foreign algorithms are compared in this paper. Then the proposed algorithm is more suitable for the implementation of VLSI. In this paper, the automatic design, verification and comprehensive platform of this algorithm will be implemented in the comprehensive results contrast analysis, and the automatic platform is used for the dynamic range. The RRNS of the 64 bit, 128 bit module group is compared.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22

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