无线多媒体传感网OFDM基带关键技术研究和VLSI实现

发布时间：2018-06-25 12:27

  本文选题：无线多媒体传感网 + OFDM基带　； 参考：《东南大学》2014年博士论文

【摘要】：无线多媒体传感器网络(WMSN)是一种感知并传递图像、音视频多媒体信息的网络,可利用多载波传输的正交频分复用(OFDM)技术频谱利用率高和抗多径衰落能力强等优点提高网络数据传输可靠性,但目前OFDM基带核心电路如信道估计与均衡、纠错、傅里叶变换等部分,存在着实现上较复杂、成本高、芯片面积大、功耗高等问题。论文综述了信道估计与均衡、纠错等关键技术的国内外研究现状,改进适用于无线多媒体传感网的信道估计与均衡、纠错算法,优化了信道估计与均衡、系统级FFT以及级联码RTL级电路,较好地降低了OFDM整体电路的复杂度与电路功耗,完成了逻辑功能仿真、FPGA验证、DC综合、后端版图设计及功耗分析。论文的主要工作与创新点：1)提出了一种适用于WMSN的高纠错能力串行级联码纠错算法,利用改进的行列分离的软入软出(SISO)交织器构造新的串行级联编译码器,在高斯和广义瑞利信道下能获得优良的纠错性能；2)改进了OFDM基带系统的LMMSE信道估计算法和MMSE均衡算法,其中该估计算法主要是借助导频值合理估算信噪比和自相关矩阵,该均衡算法通过精选插值算法由部分均衡系数可获得均衡器所有抽头系数。改进后的信道估计与均衡算法复杂度得到降低,以适应无线多媒体传感网系统低功耗要求；3)在信道均衡与估计的电路设计中,构建了改进型部分并行架构乘法器,通过对乘法运算进行操作数多级移位和分级处理,使乘法器整体硬件消耗降低约40%；在FFT电路实现中,提出了一种基于分裂基FFT算法的改进型基2/4蝶形单元处理方法,通过加法器复用、中间寄存器插入和流水线架构,使得加法器的数量缩减了30%,提高了基带系统的处理速度；4)纠错级联码电路设计上,采用全局复用方法对RS码译码器中求逆单元进行设计,并在RS码、卷积码构造的级联码结构映射方面采用多级流水线技术、时分复用方法等,减少了译码电路关键路径延时、时钟周期数等,有效降低了译码电路的功耗,使级联码整体的异或门数量减少了20.8%；优化了RS译码时关键方程求解单元的电路,使其乘法器数量减少了23.5%；充分利用分时复用和优化设计数据转移控制电路,使得卷积码译码器中的加比选单元和路径度量存储单元的数量减少一半,满足了电路低功耗要求。论文基于台积电公司TSMC 0.13μm 1.2V CMOS工艺设计了信道估计与均衡器、级联纠错译码器和FFT/IFFT模块,其中信道估计与均衡、级联纠错编译码、FFT电路这三大模块的电路面积分别为0.503mm2、0.435mm2、1.008mm2,它们对应的功耗分别为2.46mW, 4.29mW、7.04mW,这三者的面积和功耗分别只占OFDM基带接收电路整体的44.8%、54.66%,较好地达到了设计的预期效果。最终把所设计这三部分关键电路嵌入到一款低功耗高速无线多媒体传感网OFDM基带芯片中,经芯片实验测试,满足误码率低于10-6@10dB信噪比时系统设计指标要求。
[Abstract]:Wireless Multimedia Sensor Network (WMSN) is a network that perceives and transmits video, audio and multimedia information. The orthogonal Frequency Division Multiplexing (OFDM) technique of multicarrier transmission can be used to improve the reliability of network data transmission, such as high spectral efficiency and strong anti-multipath fading ability. But at present, OFDM baseband core circuits such as channel estimation and equalization, error correction, etc. There are many problems in Fourier transform, such as complex implementation, high cost, large chip area and high power consumption. This paper summarizes the research status of key technologies such as channel estimation and equalization, error correction and so on, and improves the channel estimation and equalization algorithm for wireless multimedia sensor networks, and optimizes channel estimation and equalization. System level FFT and concatenated code RTL level circuits can reduce the complexity and power consumption of OFDM circuits. The logic function simulation and FPGA verification of DC synthesis, back-end layout design and power analysis are completed. The main work and innovation of this paper are as follows: (1) A novel serial concatenated code correction algorithm with high error-correcting capability for WMSN is proposed. A new serial concatenated codec is constructed by using the improved SISO Interleaver. The LMMSE channel estimation algorithm and the MMSE equalization algorithm for OFDM baseband systems are improved, in which the SNR and autocorrelation matrix are estimated reasonably by means of pilot values. All tap coefficients of equalizer can be obtained from partial equalization coefficients by selecting interpolation algorithm. The complexity of the improved channel estimation and equalization algorithm is reduced to meet the requirement of low power consumption in wireless multimedia sensor network systems. In the circuit design of channel equalization and estimation, an improved partially parallel architecture multiplier is constructed. By multistage shift and hierarchical processing of multiplication operation, the overall hardware consumption of multiplier is reduced by 40%. In the implementation of FFT circuit, an improved 2 / 4 butterfly unit processing method based on split radix FFT algorithm is proposed. By multiplexing adders, inserting intermediate registers and pipelining architecture, the number of adders is reduced by 30%, and the processing speed of baseband system is improved. 4) the design of error-correcting concatenated code circuit. The inverse unit in RS decoder is designed by using global multiplexing method. In the aspect of structure mapping of concatenated codes constructed by RS code and convolutional code, multistage pipeline technique and time division multiplexing method are used to reduce the critical path delay of decoding circuit. The number of clock cycles can effectively reduce the power consumption of the decoding circuit and reduce the number of XOR gates in the whole concatenated code by 20.8.The circuit of the key equation solving unit in RS decoding is optimized, and the number of multiplicators is reduced by 23.5. By making full use of time-sharing multiplexing and optimizing the design of data transfer control circuits, the number of Gaby selecting units and path measurement memory cells in convolutional code decoder is reduced by half, which meets the low power requirement of the circuit. Based on TSMC 0.13 渭 m 1.2V CMOS process, channel estimation and equalizer, concatenated error correction decoder and FFT / Ifft module are designed in this paper. The circuit area of the three modules of concatenated error correction code and decode FFT circuit is 0.503mm 2n / 0.435mm / 2 and 1.008mm / 2 respectively, and their corresponding power consumption is 2.46mW and 4.29mW / 7.04mW respectively. The area and power consumption of the three modules are only 44.8854.66mW of the whole OFDM baseband receiving circuit. Finally, the three key circuits are embedded into an OFDM baseband chip with low power consumption and high speed wireless multimedia sensor network. The experiment results show that the BER is lower than 10-610dB SNR.
【学位授予单位】：东南大学
【学位级别】：博士
【学位授予年份】：2014
【分类号】：TN919.8;TP212.9
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本文编号：2065914