一种CMOS电荷泵锁相环设计

发布时间：2018-06-29 13:10

本文选题：锁相环 + 相位噪声　；参考：《电子科技大学》2014年硕士论文

【摘要】：锁相环是通信系统的重要模块,锁相环的性能在很大程度上制约着通信系统的整体性能,本文以802.11.b为应用背景,围绕电荷泵锁相环的原理、相位和噪声模型、电路设计等方面进行如下研究:阐述了锁相环的历史发展脉络和背景意义,分析了电荷泵锁相环的原理及时域相位模型,分析并讨论了电荷泵锁相环噪声性能和环路参数。阐述了压控振荡器、分频器、鉴频鉴相器、电荷泵及环路滤波器的一般结构、工作原理和数学模型,并推导一些重要的的数学公式。介绍了设计这些模块可能要注意的问题。详细介绍了本文设计的亚采样锁相环原理和结构,阐述了亚采样鉴相器的原理和数学模型,分析了亚采样电荷锁相环的噪声性能和时域相位模型,阐述了一般亚采样锁相环结构的环路滤波器电容面积过大的问题和解决方法。在上述基础之上,本文提出了一种双环路鉴相增益可调的亚采样电荷泵锁相环设计方案,其核心环路和FLL环路的鉴相增益都可以调节,这使得该锁相环抗PVT变化能力更强,良率更高。本文采用宏力GSMC 0.18μm工艺完成亚采样电荷泵锁相环各电路模块原理图设计、版图设计和性能仿真。由于GSMC 0.18μm工艺没有提供电感模型,本文选择了环形振荡器做为锁相环的压控振荡器。为了减少压控振荡器的调谐增益,本文设计了8段调谐曲线的压控振荡器,该压控振荡器的调谐增益为200MHz/V,其频率范围达到1.2GHz~2.8GHz。在FLL环路的电荷泵设计中,采用了电流在5μA-155μA可调的设计,该电流大小由数字信号控制调节,可以减小其受PVT变化的影响。仿真的结果表明该锁相环的功耗为8mW,在2.4GHz处的锁定时间为12μs,其压控振荡器的噪声性能为-94.6dBc/Hz@1MHz,锁相环的整体相位噪声为-108dBc/Hz@10KHz。
[Abstract]:Phase locked loop (PLL) is an important module of communication system. The performance of PLL restricts the whole performance of communication system to a great extent. In this paper, based on 802.11.b application background, the principle, phase and noise model of CPPLL are discussed. The circuit design is studied as follows: the history and background significance of PLL are expounded, the principle and time-domain phase model of CPPLL are analyzed, and the noise performance and loop parameters of CPPLL are analyzed and discussed. The general structure, working principle and mathematical model of voltage-controlled oscillator, frequency divider, frequency discriminator, charge pump and loop filter are described, and some important mathematical formulas are deduced. The problems that may be noticed in the design of these modules are introduced. The principle and structure of sub-sampling phase-locked loop designed in this paper are introduced in detail. The principle and mathematical model of sub-sampling phase-locked loop are described. The noise performance and time-domain phase model of sub-sampling charge phase-locked loop are analyzed. In this paper, the problem of the capacitor area of the general subsampling PLL loop filter is discussed and its solution is presented. On the basis of the above, a design scheme of sub-sampling charge pump phase-locked loop with adjustable phase discriminant gain is proposed. The phase detection gain of the core loop and FLL loop can be adjusted, which makes the phase-locked loop more resistant to PVT changes. The yield is higher. In this paper, the principle diagram design, layout design and performance simulation of sub-sampling charge pump phase-locked loop are completed by using GSMC 0.18 渭 m process. Because the GSMC 0.18 渭 m process does not provide the inductance model, the ring oscillator is chosen as the voltage-controlled oscillator of the phase-locked loop. In order to reduce the tuning gain of the VCO, a voltage-controlled oscillator with eight tuning curves is designed. The tuning gain of the VCO is 200MHz / V, and its frequency range is 1.2 GHz ~ 2.8GHz. In the design of charge pump in FLL loop, the current can be adjusted from 5 渭 to 155 渭 A, and the current is controlled by digital signal, which can reduce the influence of PVT. The simulation results show that the power consumption of the PLL is 8mW, the locking time at 2.4GHz is 12 渭 s, the noise performance of the VCO is -94.6 dBcr / Hz @ 1MHz, and the overall phase noise of PLL is -108dBc / Hz @ 10KHz.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8;TN432

【共引文献】