硅基微显示器关键存储器技术研究

发布时间：2018-07-08 13:33

本文选题：硅基微型显示器 + 计算型存储器　；参考：《上海大学》2014年博士论文

【摘要】：微型显示器由于体积小、重量轻、功耗低而成为理想便携式、可穿戴式显示器的首选。在各类微型显示器中，以单晶硅为基底的硅基OLED微型显示器由于其较高的载流子迁移率和成熟的CMOS集成电路设计技术，能够在硅芯片上集成高密度的有源寻址矩阵、周边驱动电路和显示控制器，可以有效地提高硅基微型显示器的像素密度、可靠性和稳定性。随着硅基芯片集成度的提高和人们对便携式设备较长的电池使用寿命的期望增加，功耗成为硅基微型显示器芯片设计中的一个相当关键的问题。本文围绕基于最优扫描算法的硅基微型显示器的关键存储器设计技术，针对存储器架构、低功耗策略等展开了深入的研究，主要研究内容包括：一、针对硅基微型显示器中图像处理逻辑与片外帧数据存储器之间的性能差异及片间驱动大电容引起的高功耗问题，本文提出了高能效的计算型存储器结构，该结构将图像处理逻辑电路与存储器电路集成到一个芯片模块上，以充分利用片内存储器的高带宽和较小的信号传输延迟，不仅提高了图形处理逻辑的并行性，而且降低了系统功耗和设计面积。二、从CMOS电路功耗模型分析入手，探寻功耗来源及影响因素，分析了各类动态功耗和静态功耗的优化技术的原理，在此基础上，，针对Flash存储器特点，提出了Flash存储器的低功耗设计策略，包括（1）采用多种系统模式（工作模式、静态模式、深睡眠模式和电源关断模式），以形成系统不同的低功耗状态；（2）采用异构电路设计方法，极大缩减了时钟反转引起的动态功耗以及时钟等待所需要的静态功耗；（3）采用低电源电压技术和多阈值电压技术，在保证系统高性能的条件下，使系统具有很低的功耗；（4）增设使能信号，在工作模式下，对非工作状态的电路子块进行休眠处理，从而降低了动态功耗，同时结合多阈值电压技术，使系统具有极低的静态功耗。三、基于低功耗策略，在架构和电路上采用基于栅漏分离电流镜的灵敏放大器技术及三环路控制LDO技术完成了一款低功耗Flash存储器电路设计。本文提出的基于栅漏分离的电流镜和高性能动态比较器，并以此构成的灵敏放大器，除保证了较高的读取精度外，由于具有较低的工作电压和读取电流，因而使功耗有明显的降低。提出的基于三环路控制的无片外电容型LDO，采用了电容耦合效应和自适应基准准技术，从而提高了响应速度使Flash存储器有着很快的上电时间，以快速进入工作状态，同时由于其较低的静态电流使其功耗较小。上述的关键电路结构，不仅适用于低压低功耗操作的Flash Memory的需求，而且对其它电路应用有着重要的参考价值。四、对硅基OLED微型显示器最优扫描系统的设计展开了研究，以此作为本文提出的计算型存储器结构和基于低功耗设计的Flash Memory的重要应用和验证平台。重点讨论了显示优化控制器和显示驱动器的设计、电路实现，版图设计及验证。由于芯片集成度比较高，本设计采用全定制方法和半定制方法相结合的设计方法，对于关键电路采用全定制方法设计，非关键电路采用半定制方法设计，设计层次为逻辑级，输出为门级网表，最后在系统顶层进行布局布线。
[Abstract]:Small displays, light weight and low power consumption have become ideal portable and wearable displays. In various micro displays, silicon based OLED micro displays based on monocrystalline silicon can integrate high density of silicon on silicon chips due to their high carrier mobility and mature CMOS integrated circuit design techniques. The active addressing matrix, the peripheral drive circuit and the display controller can effectively improve the pixel density, reliability and stability of the silicon based micro display. With the improvement of the silicon based chip integration and the increasing expectation of the longer battery life of the portable devices, the power consumption has become one of the design of the silicon based micro display chip. This paper focuses on the key memory design technology of the silicon based micro display based on the optimal scanning algorithm, and has carried out a deep research on the memory architecture and low power strategy. The main research contents include:
First, in view of the performance difference between the image processing logic and the outer frame data memory in the silicon based micro display and the high power consumption caused by the large capacitance of the chip drive, this paper presents a highly efficient computational memory structure which integrates the image processing logic circuit and the memory circuit to a chip module to fully profit. The high bandwidth and smaller signal transmission delay of the chip storage device not only enhance the parallelism of the graphics processing logic, but also reduce the system power consumption and the design area.
Two, from the analysis of the CMOS circuit power model, the power source and the influencing factors are explored, and the principle of the optimization technology of all kinds of dynamic and static power is analyzed. On this basis, the low power design strategy of the Flash memory is proposed for the characteristics of the Flash memory, including (1) using a variety of system modes (working mode, static mode, depth) Sleep mode and power switch mode) to form different low power state of the system; (2) the use of isomeric circuit design method greatly reduces the dynamic power consumption caused by clock reversal and the static power consumption required by the clock waiting; (3) using low power supply voltage technology and multi threshold voltage technology, under the condition of ensuring the high performance of the system, The system has very low power consumption; (4) the power signal is added, and the non working circuit subblock is dormant under the working mode, which reduces the dynamic power consumption and combines the multi threshold voltage technology to make the system very low static power.
Three, based on the low power consumption strategy, a low power Flash memory circuit is designed by using the sensitive amplifier technology based on the gate leakage separation current mirror and the three loop control LDO technology. The current mirror and the high performance dynamic comparator based on the gate leakage separation are proposed, and the sensitive amplifier which is made up of this method is guaranteed. In addition to the higher reading accuracy, the power consumption is significantly reduced because of the low working voltage and reading current. The proposed three loop based non chip capacitive LDO, which uses the capacitive coupling effect and the adaptive datum quasi technology, improves the response speed to make the Flash memory have a very fast power up time, and fast. The key circuit structure mentioned above is not only applicable to the demand of Flash Memory for low voltage and low power operation, but also has important reference value for other circuit applications.
Four, the design of the optimal scanning system for silicon based OLED micro display is studied. As an important application and verification platform for the computational memory structure and Flash Memory based on low power design, the design, circuit implementation, layout design and verification of the display optimization controller and display driver are discussed. The integration degree of chip is high. This design adopts a design method combining full custom method with semi customizing method. The design method is designed with full custom method for key circuits. Semi custom method is used to design non key circuits. The design level is logic level, output is gate level net table, and finally the layout and wiring at the top layer of the system are carried out.
【学位授予单位】：上海大学
【学位级别】：博士
【学位授予年份】：2014
【分类号】：TN873;TP333

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