步进频率连续波雷达信号处理硬件设计

发布时间：2018-07-12 15:14

本文选题：步进频率 + 雷达　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：步进频率连续波雷达采用窄带单频率步进的连续波来实现超宽带,具有系统结构和信号处理简单、发射功率低、瞬时带宽窄、等效工作带宽宽、测距和测速精度高等特点,广泛应用于探地、战场监视、微变形监测、生命探测、车辆防撞等领域。本文基于某雷达工程项目,详细研究某步进频率连续波雷达信号处理的硬件设计以及FPGA主要模块的软件设计。首先提出了基于“DSP+FPGA”双核架构的雷达信号处理机的设计架构,设计并实现了信号处理机硬件,其中包括FPGA、DSP、复位控制、时钟管理、电源管理、ADC、存储器、通信接口等模块电路。其次,设计了FPGA主要模块的软件,包括时钟与复位管理、数字下变频、加窗FFT、链路口通信、异步串口通信和以太网通信等模块的软件。最后,对信号处理机的硬件和软件进行了测试,给出了测试方法和测试结果,测试结果表明,雷达信号处理机硬件和软件设计正确,满足设计要求。
[Abstract]:Step frequency continuous wave radar uses narrow band single frequency step continuous wave to realize UWB. It has the characteristics of simple system structure and signal processing, low transmitting power, narrow instantaneous band width, wide equivalent working bandwidth, high ranging and measuring accuracy, etc. Widely used in earth exploration, battlefield surveillance, micro deformation monitoring, life detection, vehicle collision prevention and other fields. Based on a radar project, the hardware design of a step frequency CW radar signal processing and the software design of the main modules of FPGA are studied in detail in this paper. Firstly, the design architecture of radar signal processor based on "DSP FPGA" dual-core architecture is presented, and the hardware of signal processor is designed and implemented, including FPGA DSPR, reset control, clock management, power management, ADC, memory, communication interface and so on. Secondly, the software of the main modules of FPGA is designed, including clock and reset management, digital downconversion, windowed FFTT, link intersection communication, asynchronous serial port communication and Ethernet communication. Finally, the hardware and software of the signal processor are tested, and the test method and test results are given. The test results show that the design of the hardware and software of the radar signal processor is correct and meets the design requirements.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN957.51

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