一种高速电荷泵锁相环的设计与实现

发布时间：2018-07-14 13:06

【摘要】：锁相环是一个可以产生稳定的时钟输出的电路。它在模拟电路中有广泛的应用。在收发器的时钟恢复电路中需要高精度的且能调节相位的时钟来恢复出接收数据;在高速微处理器中,也需要锁相环来产生内部需要的高频时钟。锁相虽然经过多年发展,结构已经很成熟,但是芯片的高速发展对锁相环电路的速度、功耗等提出了更高的要求。因此,对锁相环进行较深人的研究,设计出性能更优越的锁相环是非常有必要的。以太网是现在使用很广泛的一种局域网。现在使用较多的还是10M/100M和千兆以太网,主要用于办公室等局域网中,它们的传输距离一般在100m内。而万兆以太网主要用于城域网,它能传输更远的距离,最远可达到40km。万兆以太网包含四个收发器,每个收发器速率已经达到3.125Gb/s,再加上长距离的传输损耗,这些对万兆以太网收发器中的PLL精度及频率提出了更高的要求,需要设计出更高精度的PLL,PLL的中心频率要达到3.125GHz。本文首先分析了锁相环的基本原理和环路传输特性。为我们接下来设计锁相环电路提供理论支持。本论文所设计的锁相环频率较高,结构采用常见的电荷泵锁相环。鉴频鉴相器我们选用的是加入延时单元的无死区鉴频鉴相器,他不仅消除了鉴相死区,并且没有反馈回路,提高了工作频率。论文提出了一种新结构的电荷泵电路,采用了一种改进型的差分式结构,加入运放器使上下电流镜电流匹配,同时加入特殊MOS管去除尖峰脉冲。滤波器采用传统的二阶滤波器,可以很好的抑制控制线上的波纹,减小输出的相位噪声。压控振荡器采用差分结构的四级环形振荡器,该振荡器具有很好的噪声性能,且输出电压幅度比较大。在分频器方面,采用SCL逻辑触发器,提高了前置分频器可工作的最高频率。最后对各个单元的电路进行仿真验证。结果表明各模块性能均满足设计的要求。本设计采用台积电0.13μm CMOS的工艺进行设计。电路设计选用1.2V电源电压。电路整体仿真结果满足我们的设计需求。
[Abstract]:A PLL is a circuit that produces a stable clock output. It is widely used in analog circuits. In the clock recovery circuit of the transceiver, a high-precision and phase-adjustable clock is needed to recover the received data; in a high-speed microprocessor, a phase-locked loop is also needed to generate the internal high-frequency clock. Although the structure of PLL has been developed for many years, the high speed development of the chip has put forward higher requirements for the speed and power consumption of PLL circuits. Therefore, it is necessary to design a phase locked loop with better performance. Ethernet is a kind of LAN which is widely used nowadays. At present, 10m / 100M and Gigabit Ethernet are mainly used in local area networks such as office, and their transmission distance is generally within 100m. Gigabit Ethernet is mainly used in metropolitan area networks, it can transmit more distance, up to 40 km. Gigabit Ethernet consists of four transceivers, each with a rate of 3.125 GB / s, and long distance transmission losses, which require higher PLL accuracy and frequency in the Gigabit Ethernet transceiver. A higher precision PLL PLL PLL needs to be designed with a center frequency of 3.125 GHz. In this paper, the basic principle and transmission characteristics of PLL are analyzed. It provides theoretical support for the design of phase locked loop circuit. The frequency of the PLL designed in this paper is high, and the common charge pump PLL is used in the structure. The phase discriminator we choose is a dead-zone phase discriminator with delay unit, which not only eliminates the dead-zone, but also has no feedback loop, which improves the working frequency. In this paper, a new type of charge pump circuit is proposed. An improved differential structure is adopted. The current of the upper and lower current mirror can be matched by adding an operational amplifier, and a special MOS transistor is added to remove the peak pulse. The filter adopts the traditional second-order filter, which can suppress the ripple on the control line and reduce the phase noise of the output. The voltage-controlled oscillator uses a four-stage ring oscillator with differential structure. The oscillator has good noise performance and the output voltage amplitude is relatively large. In the frequency divider, SCL logic trigger is used to improve the maximum frequency of the predivider. Finally, the circuit of each unit is simulated and verified. The results show that the performance of each module meets the requirements of the design. The design is based on TSMC 0.13 渭 m CMOS process. 1.2V power supply voltage is selected for circuit design. The whole circuit simulation results meet our design requirements.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8

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