高速可定时数据合成模块设计

发布时间：2018-07-16 12:51

【摘要】：数据发生器作为现代测试与控制中常用的信号源,它可以产生具有一定编码规则的用户数据,用来满足特定数据测试要求。随着现代科技水平的快速发展,待测设备的工作速度不断提高以及系统功能更加复杂化,相应的对数据发生器提出了高数据率、深存储度、可编程能力、多触发方式、皮秒定时等要求。本课题研究高速数据流合成技术,完成高速可定时数据合成模块设计,最终实现2.7Gbps串行数据流输出和单通道256Mbits存储深度的双通道高速数据流合成系统。高速可定时数据合成模块作为数据发生器的核心单元,担负着实现仪器的大部分功能和指标的任务。主要包括:产生两通道串行数据流信号,实现重复、单次、单步三种工作模式以及数据率、定时延迟参数均可调的功能。本文阐述了如何产生数据率高、存储深度深并工作在多种模式下的无缝数据流。具体工作内容如下:(1)阐述高速数据流合成的基本原理和方法,结合功能和指标要求,分析高速数据流合成的设计难点,提出高速可定时数据合成模块的总体设计方案。(2)完成时钟单元电路设计,采用DDS和锁相环相结合的方式实现频率范围为50KHz~2.7GHz的差分时钟输出。(3)完成数据合成和控制单元电路。采用DDR存储技术并结合FIFO缓冲数据的方法,完成无缝深存储数据的产生。其中以DDR存储器的大容量实现256Mbits的深存储,以FIFO的缓冲来完成数据的速率转接和控制重部,利用并串转换技术实现最高2.7Gbps数据率;采用高分辨率的可编程延迟线器件组来实现双通道延迟定时的准确性和高分辨率。(4)根据各单元模块产生的信号波形测试图,分析实际工作状况。对在调试中遇见的问题进行分析,给出解决这些问题所使用的方法。最后完成高速可定时数据合成模块的测试与验收,并整理相关技术文档。本文通过对上述重点技术的研究实现,完成了高速可定时数据合成模块的设计与调试,实现了在多种触发方式和运行模式下的高速数据流输出,达到了设计所要求的目标。
[Abstract]:As a common signal source in modern testing and control, data generator can generate user data with certain coding rules to meet the requirements of specific data testing. With the rapid development of modern science and technology, the working speed of the equipment to be tested has been improved and the system function has become more complicated. Accordingly, the high data rate, deep storage, programmable ability and multi-trigger mode are proposed for the data generator. Picosecond timing and other requirements. In this paper, the high speed data stream synthesis technology is studied, and the design of high speed timing data synthesis module is completed. Finally, a 2. 7Gbps serial data stream output and a single channel 256Mbits storage depth two channel high speed data stream synthesis system are realized. As the core unit of the data generator, the high speed timing data synthesis module is responsible for realizing most of the functions and targets of the instrument. It mainly includes: generating two channel serial data stream signals, realizing the functions of repeat, single, single step, data rate and timing delay parameters can be adjusted. This paper describes how to generate a seamless data stream with high data rate, deep storage depth and working in multiple modes. The main contents are as follows: (1) the basic principles and methods of high speed data stream synthesis are expounded, and the design difficulties of high speed data stream synthesis are analyzed according to the function and index requirements. The overall design scheme of high speed timing data synthesis module is presented. (2) the clock unit circuit is designed and the differential clock output with the frequency range of 50 KHz 2.7GHz is realized by combining DDS and PLL. (3) the data synthesis and control unit circuit is completed. Using DDR storage technology and FIFO buffer data, the generation of seamless deep storage data is completed. The DDR memory is used to realize 256Mbits deep storage, the FIFO buffer is used to complete the data rate transfer and control reconfiguration, and the data rate is up to 2.7Gbps using parallel string conversion technology. The high resolution programmable delay line device group is used to realize the accuracy and high resolution of dual channel delay timing. (4) according to the signal waveform test diagram generated by each unit module, the actual working condition is analyzed. The problems encountered in debugging are analyzed, and the methods to solve these problems are given. Finally, the test and acceptance of the high-speed timing data synthesis module are completed, and the related technical documents are arranged. Through the research and implementation of the above key technologies, the design and debugging of the high speed timing data synthesis module are completed, and the output of the high speed data stream under various trigger modes and operation modes is realized, and the goal of the design is achieved.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN929.53

【相似文献】