面向光纤通道的SerDes电路IP化技术研究

发布时间：2018-07-17 04:00

【摘要】：随着日益增长的高速传输的需要,传统的并行通信技术已经成为进一步提高数据传输速率的主要瓶颈,限制了系统整体性能的提升。在这种情况下,以SerDes为代表的串行通信技术以其较低的功耗、简单的系统互联、更强的抗干扰能力以及更高的传输速率等优点,正在逐步取代传统的并行通信技术而成为当前高速通信的主流。SerDes是英文Serializer(串化器)/Deserializer(解串器)的缩写。在发送端,用于将低速的并行CMOS数字信号转换为高速的串行低电压差分信号并通过光纤或铜线发送出去;在接收端,再将高速的低电压差分信号正确的转换为CMOS电平信号后进行串并转换输出。它是一种时分多用、点对点的串行通信技术,广泛应用于光纤通信、接入设备、WI系统以及工业控制系统。这种点对点的串行通信技术不需要传输同步时钟,所以传输速率可以达到很高,而且互连时最少只需要一对传输线,可以有效减少系统互连的复杂度,降低总体成本。一个典型的SerDes芯片包括:8B/10B编解码器、产生高速时钟的锁相环、LVDS收发器以及从接收信号中恢复出时钟的CDR电路。本文旨在研究SerDes电路的IP化并将其用于光纤通信的物理层接口中。围绕SerDes电路IP化所要交付的内容,做了如下一些工作:第一,详细研究了IP化流程,IP软核、固核和硬核的异同以及它们在IP化过程中所要提交的内容;第二,详细研究了SerDes电路的原理图、版图以及特殊I/O;第三,采用模拟硬件描述语言Verilog-A对SerDes进行行为建模;第四,采用Synopsys的NanoTime对Ser Des进行时序建模。最后,以0.13μm CMOS工艺实现的一款工作在0.5-1.5Gb/s速率的SerDes芯片为基础,全面测试了其性能。实际测试表明,所建立的模型与实际芯片的测试结果相吻合。本文的研究成果期冀于为后续的SerDes芯片以IP的形式集成到光纤通信的物理层接口中提供参考价值以及研究基础。
[Abstract]:With the increasing demand of high-speed transmission, the traditional parallel communication technology has become the main bottleneck to further improve the data transmission rate, which limits the overall performance of the system. In this case, the serial communication technology represented by SerDes has the advantages of low power consumption, simple system interconnection, stronger anti-interference ability and higher transmission rate, etc. It is gradually replacing the traditional parallel communication technology to become the mainstream of high speed communication. SerDes is the abbreviation of Serializer / Deserializer. At the transmitter, it is used to convert a low-speed parallel CMOS digital signal to a high-speed serial low-voltage differential signal and transmit it through optical fiber or copper wire; at the receiving end, Then the high-speed low-voltage differential signal is converted to CMOS level signal correctly and then serially converted to output. It is a kind of time division multipurpose, point to point serial communication technology, which is widely used in optical fiber communication, access equipment and industrial control system. This kind of point-to-point serial communication technology does not need to transmit synchronous clock, so the transmission rate can reach very high, and only a pair of transmission lines are required for interconnection, which can effectively reduce the complexity of system interconnection and reduce the overall cost. A typical SerDes chip includes a: 8B / 10B codec, a phase-locked loop LVDS transceiver that generates a high speed clock, and a CDR circuit that recovers the clock from the received signal. The purpose of this paper is to study the IP of Serdes circuit and use it in the physical layer interface of optical fiber communication. Some work has been done around the contents of the IP of SerDes circuit. First, the IP soft core, the similarities and differences between the fixed core and the hard core, and the contents to be submitted in the IP process are studied in detail. The schematic diagram, layout and special I / O of SerDes circuit are studied in detail. Thirdly, SerDes is modeled with the analog hardware description language Verilog-A; fourth, the sequential modeling of SerDes is done by using Synopsys NanoTime. Finally, based on a 0.13 渭 m CMOS SerDes chip operating at 0.5-1.5 GB / s rate, the performance of the chip is tested. The actual test results show that the model is in agreement with the actual chip test results. The research results in this paper are expected to provide reference value and research basis for the subsequent SerDes chip to be integrated into the physical layer interface of optical fiber communication in the form of IP.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN929.11

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