高速SERDES接口建模与锁相环设计
发布时间：2018-08-13 20:48
【摘要】：随着通讯技术的发展,并行传输方式已经难以满足带宽和功耗等要求,串行传输方式由于传输速度快、功耗低和抗干扰能力强等优点,成为主流的传输方式。SERDES接口能够实现并行与串行相互转换的功能,成为主流的传输接口。其中,8B/10B SERDES由于具有直流平衡和易于交流耦合等优点,成为接口电路研究的热点。本文介绍了SERDES系统架构的四种实现方式,并根据各自的优缺点,选定了8B/10B SERDES为研究对象,详细分析与介绍了SERDES系统中的各个模块的工作原理,包括并串转换电路、半速率时钟选择电路、占空比1：5的五分频电路和串并转换电路等。最后按照发送通道与接收通道对系统进行了Simulink建模。在并行信号输入时钟频率为250MHz时,输出信号频率可达到2.5Gbps。电荷泵锁相环(CPPLL)作为8B/10B SERDES中的重要组成部分,为整个系统提供时钟,其性能将直接影响传输精度。本文对电荷泵锁相环的各个组成部分进行了理论和非理想因素分析,并给出了本文的电路设计与非理想因素解决方法。最后在1.2/2.5V电源电压下,使用SMIC 65nm CMOS工艺,对电荷泵锁相环进行了仿真与分析。由仿真结果可以得知,在输入信号频率为100MHz时,CPPLL稳定输出2.5GHz时钟信号,锁定时间仅需0.6us,符合SERDES系统对CPPLL的性能要求。
[Abstract]:With the development of communication technology, the parallel transmission mode has been difficult to meet the requirements of bandwidth and power consumption. The serial transmission mode has the advantages of high transmission speed, low power consumption and strong anti-interference ability. The main transmission mode. SERDES interface can realize the function of parallel and serial conversion and become the mainstream transmission interface. Among them, 8B / 10B SERDES has the advantages of DC balance and easy AC coupling, so it has become a hotspot in the research of interface circuits. This paper introduces four realization methods of SERDES system architecture, and selects 8B/10B SERDES as the research object according to their advantages and disadvantages. The working principle of each module in SERDES system is analyzed and introduced in detail, including parallel series conversion circuit. Half-rate clock selection circuit, duty cycle 1:5 five-frequency circuit and serial-parallel conversion circuit. Finally, the Simulink model of the system is built according to the transmission channel and the receiving channel. When the input clock frequency of the parallel signal is 250MHz, the output signal frequency can reach 2.5 Gbps. As an important part of 8B/10B SERDES, the charge pump PLL (CPPLL) provides the clock for the whole system, and its performance will directly affect the transmission accuracy. In this paper, the various components of the charge pump phase-locked loop are analyzed theoretically and the non-ideal factors are analyzed, and the circuit design and the solution of the non-ideal factors are given. Finally, the charge pump PLL is simulated and analyzed at 1.2 / 2.5V power supply voltage using SMIC 65nm CMOS process. The simulation results show that the 2.5GHz clock signal is output stably when the input signal frequency is 100MHz, and the locking time is only 0.6 us.This meets the performance requirements of SERDES system for CPPLL.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN911.8
本文编号：2182142
[Abstract]:With the development of communication technology, the parallel transmission mode has been difficult to meet the requirements of bandwidth and power consumption. The serial transmission mode has the advantages of high transmission speed, low power consumption and strong anti-interference ability. The main transmission mode. SERDES interface can realize the function of parallel and serial conversion and become the mainstream transmission interface. Among them, 8B / 10B SERDES has the advantages of DC balance and easy AC coupling, so it has become a hotspot in the research of interface circuits. This paper introduces four realization methods of SERDES system architecture, and selects 8B/10B SERDES as the research object according to their advantages and disadvantages. The working principle of each module in SERDES system is analyzed and introduced in detail, including parallel series conversion circuit. Half-rate clock selection circuit, duty cycle 1:5 five-frequency circuit and serial-parallel conversion circuit. Finally, the Simulink model of the system is built according to the transmission channel and the receiving channel. When the input clock frequency of the parallel signal is 250MHz, the output signal frequency can reach 2.5 Gbps. As an important part of 8B/10B SERDES, the charge pump PLL (CPPLL) provides the clock for the whole system, and its performance will directly affect the transmission accuracy. In this paper, the various components of the charge pump phase-locked loop are analyzed theoretically and the non-ideal factors are analyzed, and the circuit design and the solution of the non-ideal factors are given. Finally, the charge pump PLL is simulated and analyzed at 1.2 / 2.5V power supply voltage using SMIC 65nm CMOS process. The simulation results show that the 2.5GHz clock signal is output stably when the input signal frequency is 100MHz, and the locking time is only 0.6 us.This meets the performance requirements of SERDES system for CPPLL.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN911.8
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