万兆级网络综合测试系统兼容接口设计与研究
发布时间：2018-08-21 20:50
【摘要】：在航空电子系统中,各个功能模块之间要传输海量的数据信息,要求总线带宽具有万兆级。同时,当今科技的发展为航空电子系统进行高速数据通信提供了多种选择,包括万兆以太网和光纤通道技术在内的COTS网络技术,可以用作航空电子总线技术的支持和补充。万兆级网络综合测试系统主要对航空电子系统网络的各项性能进行测试与调试。本文进行了万兆级网络综合测试系统兼容接口的设计,其目标是实现万兆以太网和光纤通道网络在物理层接口处的兼容。对比分析了万兆以太网和光纤通道网络物理层规范标准,说明了接口兼容设计的可行性。兼容接口设计的内容包括硬件接口电路和兼容接口逻辑功能模块,硬件接口电路设计能够支持1/10GE和1/2/4/8GFC的数据传输。对比分析了X2和SFP+光收发器的基本性能和应用特点,选择了同时服从万兆以太网和光纤通道网络协议标准的SFP+光收发器。根据兼容性设计要求,选择了单通道和四通道的时钟数据恢复器。本文完成了硬件接口电路原理图和PCB设计。兼容接口逻辑功能模块包括兼容接口逻辑处理模块、XGMII改进接口、时钟管理单元和数据管理单元,能够实现万兆以太网和光纤通道物理层数据的处理。兼容接口逻辑处理模块改进了GTX IPCore,采用了GTX的SerDes功能模块,主要实现兼容接口的逻辑功能。XGMII改进接口能够支持不同速率以太网和光纤通道网络的数据传输,时钟管理单元负责时钟同步和提供参考时钟,数据管理单元负责控制信号的配置管理。本文完成了兼容接口的功能验证,包括在开发板上对接口的兼容性进行验证和在Modelsim上对兼容性模块进行功能仿真。改进的GTX在开发板上实现了对不同速率网络的支持。仿真验证的逻辑功能模块包括SerDes模块、编解码模块、CRC校验模块、扰码解扰码模块、FC端口状态机模块、XGMII改进接口以及10G MAC模块。接口兼容性功能验证说明了兼容接口设计的正确性。本文的兼容接口设计初步实现了万兆以太网和光纤通道网络物理层的融合。
[Abstract]:In avionics system, there is a huge amount of data information to be transmitted between each functional module, which requires a bus bandwidth of ten thousand megabytes. At the same time, the development of science and technology provides a variety of options for high-speed data communication in avionics systems. The COTS network technology, including Gigabit Ethernet and fiber channel technology, can be used as the support and supplement of avionics bus technology. The multimegabit network integrated test system mainly tests and debugs the performance of avionics system network. In this paper, the compatible interface of the multi-megabyte network test system is designed. The goal is to realize the compatibility between the Ethernet and the fiber channel network at the interface of the physical layer. This paper compares and analyzes the physical layer specification standards of ten thousand megabit Ethernet and fiber channel network, and explains the feasibility of interface compatibility design. The content of compatible interface design includes hardware interface circuit and compatible interface logic module. Hardware interface circuit design can support data transmission between 1/10GE and 1/2/4/8GFC. The basic performance and application characteristics of X2 and SFP optical transceivers are compared and analyzed. The SFP optical transceivers serving both slave Ethernet and fiber channel network protocol standards are selected. According to the requirements of compatibility design, single channel and four channel clock data restorer are selected. In this paper, the hardware interface circuit schematic diagram and PCB design are completed. The compatible interface logic module includes compatible interface logic processing module XGMII improved interface, clock management unit and data management unit, which can realize the data processing in the physical layer of Gigabit Ethernet and optical fiber channel. The compatible interface logic processing module improves the GTX IP Core, and adopts the SerDes function module of GTX. It mainly realizes the compatible interface logic function. XGMII improved interface can support the data transmission of Ethernet and fiber channel network with different rates. The clock management unit is responsible for clock synchronization and reference clock, and the data management unit is responsible for the configuration management of the control signal. This paper completes the functional verification of the compatible interface, including verification of the compatibility of the interface on the development board and functional simulation of the compatibility module on the Modelsim. The improved GTX supports different rate networks on the development board. The logic function modules include SerDes module, encoding and decoding module, scrambling code unscrambling module, FC port state machine module and 10G MAC module. The verification of interface compatibility function shows the correctness of compatible interface design. The compatible interface design of this paper primarily realizes the fusion of the physical layer of the Ethernet and the fiber channel network.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：V243;TN915.06
本文编号：2196313
[Abstract]:In avionics system, there is a huge amount of data information to be transmitted between each functional module, which requires a bus bandwidth of ten thousand megabytes. At the same time, the development of science and technology provides a variety of options for high-speed data communication in avionics systems. The COTS network technology, including Gigabit Ethernet and fiber channel technology, can be used as the support and supplement of avionics bus technology. The multimegabit network integrated test system mainly tests and debugs the performance of avionics system network. In this paper, the compatible interface of the multi-megabyte network test system is designed. The goal is to realize the compatibility between the Ethernet and the fiber channel network at the interface of the physical layer. This paper compares and analyzes the physical layer specification standards of ten thousand megabit Ethernet and fiber channel network, and explains the feasibility of interface compatibility design. The content of compatible interface design includes hardware interface circuit and compatible interface logic module. Hardware interface circuit design can support data transmission between 1/10GE and 1/2/4/8GFC. The basic performance and application characteristics of X2 and SFP optical transceivers are compared and analyzed. The SFP optical transceivers serving both slave Ethernet and fiber channel network protocol standards are selected. According to the requirements of compatibility design, single channel and four channel clock data restorer are selected. In this paper, the hardware interface circuit schematic diagram and PCB design are completed. The compatible interface logic module includes compatible interface logic processing module XGMII improved interface, clock management unit and data management unit, which can realize the data processing in the physical layer of Gigabit Ethernet and optical fiber channel. The compatible interface logic processing module improves the GTX IP Core, and adopts the SerDes function module of GTX. It mainly realizes the compatible interface logic function. XGMII improved interface can support the data transmission of Ethernet and fiber channel network with different rates. The clock management unit is responsible for clock synchronization and reference clock, and the data management unit is responsible for the configuration management of the control signal. This paper completes the functional verification of the compatible interface, including verification of the compatibility of the interface on the development board and functional simulation of the compatibility module on the Modelsim. The improved GTX supports different rate networks on the development board. The logic function modules include SerDes module, encoding and decoding module, scrambling code unscrambling module, FC port state machine module and 10G MAC module. The verification of interface compatibility function shows the correctness of compatible interface design. The compatible interface design of this paper primarily realizes the fusion of the physical layer of the Ethernet and the fiber channel network.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：V243;TN915.06
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，本文编号：2196313
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