HEVC标准中整数变换的FPGA实现
发布时间：2018-08-27 08:09
【摘要】：新一代视频编码标准(High Efficiency Video Coding,HEVC)中整数DCT编码支持大小从4×4到32×32的TU块,运算量巨大。通过优化MCM单元来减少运算量,通过硬件电路复用来减少硬件资源消耗,同时使用转置模块来加速流水线,并且能适应各种不同大小的TU块。实验代码通过Verilog HDL编写,并在Altera Arria GX EP1AGX90EF1152C FPGA上综合。结果表明,该结构等待时延最多为32个时钟周期,每个时钟周期能处理32个采样点,在184 MHz的时钟频率下,能实时处理60 f/s(帧/秒)的UHD(Ultra-High-Definition 7 680×4 320)视频信号。
[Abstract]:In the next generation of video coding standard (High Efficiency Video Coding,HEVC), integer DCT coding supports TU blocks ranging from 4 脳 4 to 32 脳 32. The MCM unit is optimized to reduce the computation cost, the hardware circuit reuse is used to reduce the hardware resource consumption, and the transpose module is used to speed up the pipeline, and it can adapt to various TU blocks of different sizes. The experimental code is written by Verilog HDL and synthesized on Altera Arria GX EP1AGX90EF1152C FPGA. The results show that the time delay of the structure is up to 32 clock cycles, and each clock cycle can process 32 sampling points. At the clock frequency of 184 MHz, the UHD (Ultra-High-Definition 7 680 脳 4 320) video signal of 60 f / s (frame / second) can be processed in real time.
【作者单位】： 福州大学工业控制研究所;
【分类号】：TN919.81
[Abstract]:In the next generation of video coding standard (High Efficiency Video Coding,HEVC), integer DCT coding supports TU blocks ranging from 4 脳 4 to 32 脳 32. The MCM unit is optimized to reduce the computation cost, the hardware circuit reuse is used to reduce the hardware resource consumption, and the transpose module is used to speed up the pipeline, and it can adapt to various TU blocks of different sizes. The experimental code is written by Verilog HDL and synthesized on Altera Arria GX EP1AGX90EF1152C FPGA. The results show that the time delay of the structure is up to 32 clock cycles, and each clock cycle can process 32 sampling points. At the clock frequency of 184 MHz, the UHD (Ultra-High-Definition 7 680 脳 4 320) video signal of 60 f / s (frame / second) can be processed in real time.
【作者单位】： 福州大学工业控制研究所;
【分类号】：TN919.81
【参考文献】
相关期刊论文 前2条
1 蔡晓霞;崔岩松;邓中亮;常志峰;;下一代视频编码标准关键技术[J];电视技术;2012年02期
2 刘毅;罗军;黄启俊;常胜;;HEVC整数DCT变换与量化的FPGA实现[J];电视技术;2013年11期
【共引文献】
相关期刊论文 前10条
1 崔遥;刘军;;HEVC关键技术介绍[J];科技创新与应用;2012年33期
2 刘毅;罗军;黄启俊;常胜;;HEVC整数DCT变换与量化的FPGA实现[J];电视技术;2013年11期
3 张玢;;高效视频编码标准中的关键技术概述[J];电脑知识与技术;2013年18期
4 原菲;司占军;顾，
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