基于CMMB标准的LDPC算法研究及电路实现
发布时间：2018-10-05 18:12
【摘要】：近年来移动终端更新换代的速度越来越快,这就对各个商家设备的性能要求越来越高。为了保证通信系统中信息的可靠传输,纠错编码是不可或缺的组成部分,在实际应用中LDPC码是众多纠错码中性能最佳的纠错码。21世纪初,国家广电总局提出我国移动多媒体规范CMMB(China Mobile Multimedia Broadcasting)。为了推广我国自主科研的成果,在全国范围内掀起了研究的热潮,此规范的前向纠错部分是LDPC码作为内码来完成的。本文不仅完成了LDPC译码算法的研究,同时对译码器进行电路实现和FPGA验证,在此基础上完成逻辑综合及布局布线的工作。本文首先对比分析了基本的译码算法,然后得到了性能更优的LDPC译码算法。一种是基于最小和算法改进的最小次小和算法,该算法简化了和积算法的复杂度,译码性能比同样简化处理的最小和算法更好;另一种是改进的分层译码算法,该算法克服了传统分层译码可靠度不均匀的缺陷,在相同误比特率条件下,性能提高了近0.5dB。本文在硬件实现过程中,分析了算法到硬件实现的映射过程,并充分考虑到面积、速率和功耗等各方面的权衡。分层译码算法实现时,一个分层中每一列的列重不能超过1。为了满足这一限制条件且实现最大并行度,需要对校验矩阵进行等价转换。面积方面,对后验概率存储、校验信息存储以及校验节点运算单元进行改进。首先,根据变换后校验矩阵的循环特点,简化了译码过程中后验信息的读写操作;其次,对校验信息进行压缩存储;最后,校验节点运算单元中采用占用面积小的基于指针的求最小次小值方法,并且改变了乘系数模块的运算顺序和运算过程,这样减少了乘系数模块的个数,提高了运算精度。速率方面,采用部分并行结构,并且对后验存储采用乒乓操作来提升速率。本文最后用VCS平台自行构建测试环境,充分保证了译码器功能的正确性,进而在Xilinx的VIRTEX-5型号FPGA上进行原型验证。该设计吞吐率为20Mbps,满足CMMB标准16Mbps的要求。后面进行的逻辑综合、布局布线工作保证了时序收敛。
[Abstract]:In recent years, the speed of upgrading mobile terminals is getting faster and faster. In order to ensure the reliable transmission of information in communication system, error-correcting coding is an indispensable part. In practical application, LDPC code is the best error-correcting code in many error-correcting codes. The State Administration of Radio, Film and Television proposes the Mobile Multimedia Standard CMMB (China Mobile Multimedia Broadcasting). In order to promote the achievements of independent scientific research in our country, there has been a nationwide upsurge of research. The forward error correction part of this standard is completed by LDPC code as internal code. In this paper, not only the research of LDPC decoding algorithm is completed, but also the circuit implementation and FPGA verification of the decoder are carried out. On this basis, logic synthesis and layout and routing are completed. In this paper, the basic decoding algorithms are compared and analyzed firstly, and then the LDPC decoding algorithm with better performance is obtained. One is an improved minimum sum algorithm based on the minimum sum algorithm, which simplifies the complexity of the sum product algorithm, and the decoding performance is better than the minimum sum algorithm, and the other is the improved hierarchical decoding algorithm. The algorithm overcomes the disadvantage of uneven reliability of traditional layered decoding, and improves performance by nearly 0.5 dB under the condition of the same bit error rate (BER). In the process of hardware implementation, the mapping process of algorithm to hardware implementation is analyzed, and the tradeoffs of area, speed and power consumption are fully considered. When the hierarchical decoding algorithm is implemented, the column weight of each column in a layer cannot exceed 1. In order to satisfy this restriction condition and realize the maximum parallelism, it is necessary to transform the check matrix equivalent. In area, the storage of posteriori probability, the storage of checkout information and the operation unit of check node are improved. Firstly, according to the cyclic characteristics of the transformed check matrix, the reading and writing operation of the posteriori information in the decoding process is simplified; secondly, the check information is compressed and stored; finally, In the operation unit of check node, the method of finding minimum value based on pointer with small occupation area is adopted, and the operation sequence and process of multiplication coefficient module are changed, which reduces the number of multiplication coefficient modules and improves the operation precision. In the aspect of rate, partial parallel structure is adopted, and ping-pong operation is used to speed up the posteriori storage. Finally, the test environment is built on VCS platform, which fully ensures the correctness of the decoder function, and then the prototype verification is carried out on the VIRTEX-5 FPGA of Xilinx. The designed throughput is 20 Mbpss, which meets the requirements of CMMB standard 16Mbps. After the logic synthesis, layout and routing to ensure the timing convergence.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN911.22
本文编号：2254372
[Abstract]:In recent years, the speed of upgrading mobile terminals is getting faster and faster. In order to ensure the reliable transmission of information in communication system, error-correcting coding is an indispensable part. In practical application, LDPC code is the best error-correcting code in many error-correcting codes. The State Administration of Radio, Film and Television proposes the Mobile Multimedia Standard CMMB (China Mobile Multimedia Broadcasting). In order to promote the achievements of independent scientific research in our country, there has been a nationwide upsurge of research. The forward error correction part of this standard is completed by LDPC code as internal code. In this paper, not only the research of LDPC decoding algorithm is completed, but also the circuit implementation and FPGA verification of the decoder are carried out. On this basis, logic synthesis and layout and routing are completed. In this paper, the basic decoding algorithms are compared and analyzed firstly, and then the LDPC decoding algorithm with better performance is obtained. One is an improved minimum sum algorithm based on the minimum sum algorithm, which simplifies the complexity of the sum product algorithm, and the decoding performance is better than the minimum sum algorithm, and the other is the improved hierarchical decoding algorithm. The algorithm overcomes the disadvantage of uneven reliability of traditional layered decoding, and improves performance by nearly 0.5 dB under the condition of the same bit error rate (BER). In the process of hardware implementation, the mapping process of algorithm to hardware implementation is analyzed, and the tradeoffs of area, speed and power consumption are fully considered. When the hierarchical decoding algorithm is implemented, the column weight of each column in a layer cannot exceed 1. In order to satisfy this restriction condition and realize the maximum parallelism, it is necessary to transform the check matrix equivalent. In area, the storage of posteriori probability, the storage of checkout information and the operation unit of check node are improved. Firstly, according to the cyclic characteristics of the transformed check matrix, the reading and writing operation of the posteriori information in the decoding process is simplified; secondly, the check information is compressed and stored; finally, In the operation unit of check node, the method of finding minimum value based on pointer with small occupation area is adopted, and the operation sequence and process of multiplication coefficient module are changed, which reduces the number of multiplication coefficient modules and improves the operation precision. In the aspect of rate, partial parallel structure is adopted, and ping-pong operation is used to speed up the posteriori storage. Finally, the test environment is built on VCS platform, which fully ensures the correctness of the decoder function, and then the prototype verification is carried out on the VIRTEX-5 FPGA of Xilinx. The designed throughput is 20 Mbpss, which meets the requirements of CMMB standard 16Mbps. After the logic synthesis, layout and routing to ensure the timing convergence.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN911.22
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相关硕士学位论文 前1条
1 程飞;CMMB物理层关键技术研究与改进[D];北京邮电大学;2009年
，本文编号：2254372
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