面向视频解码应用的SOPC系统研究

发布时间：2018-10-20 14:36

【摘要】：随着科技发展,视频应用不断地得到普及,改变着我们的生活、交流和工作方式。而未经压缩处理的视频数据量往往很大,不便于存储和传输,因此需要进行视频压缩编码来减少冗余信息。而H.264是常用的视频压缩标准之一,它具有压缩率高,信噪比高等优点,尤其适合低码率视频应用场合。H.264视频解码有多种实现方案,常见的有基于通用处理器、基于ASIC、基于DSP和基于GPU等。本文则基于FPGA采用SOPC的方式实现H.264视频解码。SOPC具有软硬件均可编程的特点,设计灵活度高,非常适合用于SOC系统的原型设计。本文先对H.264视频编解码技术和基于FPGA的SOPC开发技术进行介绍。然后以在Xilinx FPGA上实现H.264低码率视频解码为目标,分析了基于软件解码和基于硬件解码的两种SOPC系统设计方案。其中,基于软件解码的SOPC系统是由Power PC处理器执行软件解码程序来完成H.264解码功能;而基于硬件解码的SOPC系统是由特定的硬件电路模块来完成H.264解码功能。在基于软件解码的SOPC系统设计中,深入研究了Xilinx的Power PC440、Crossbar、MPMC和tft controller等IP核,并在XPS开发环境下,利用这些IP核搭建了一个能运行操作系统和支持视频输出显示的嵌入式系统硬件平台。通过在基于Power PC的嵌入式系统硬件平台上移植Linux操作系统,并在Linux上运行开源软件解码程序MPlayer,用软件方式实现了H.264视频解码和输出显示。在基于硬件解码的SOPC系统设计中,通过集成第三方H.264硬件解码IP核,用硬件方式实现基本档次(Baseline Profile)的H.264视频解码,软件部分完成视频输出显示。本文基于Modelsim对第三方IP核的功能进行仿真验证,然后详细讨论了在XPS中集成自定义IP核的过程,包括实现PLB接口,建立IP核目录和利用Chip Scope进行调试等方面。经实验测试,利用第三方硬件解码IP核,能完成基本档次的QCIF大小的H.264视频实时解码。此外,本文给出了一种软硬件相结合的H.264解码器的硬件架构,并用Verilog语言完成了其中的CAVLC熵解码子模块的设计,在Modelsim上进行仿真验证,仿真结果表明模块功能正确。
[Abstract]:With the development of science and technology, video applications are becoming more and more popular, changing the way we live, communicate and work. However, the amount of uncompressed video data is often very large, which is not convenient for storage and transmission, so video compression coding is needed to reduce redundant information. H.264 is one of the commonly used video compression standards. It has the advantages of high compression rate and high signal-to-noise ratio, especially for low bit-rate video applications. Based on ASIC, based on DSP and based on GPU. In this paper, H.264 video decoding is realized by SOPC based on FPGA. SOPC has the characteristics of programmable software and hardware, and high design flexibility, so it is very suitable for the prototype design of SOC system. This paper first introduces H.264 video coding and decoding technology and SOPC development technology based on FPGA. Then, aiming at the realization of H.264 low bit-rate video decoding on Xilinx FPGA, two kinds of SOPC system design schemes based on software decoding and hardware decoding are analyzed. In the SOPC system based on software decoding, the software decoding program is executed by the Power PC processor, while the SOPC system based on the hardware decoding is completed by the specific hardware circuit module. In the design of SOPC system based on software decoding, the IP cores such as Power PC440,Crossbar,MPMC and tft controller of Xilinx are deeply studied, and in the XPS development environment, Using these IP cores, an embedded system hardware platform which can run the operating system and support video output display is built. By transplanting the Linux operating system on the embedded system hardware platform based on Power PC, and running the open source software decoding program MPlayer, on the Linux, the H.264 video decoding and output display are realized by software. In the design of SOPC system based on hardware decoding, the H.264 video decoding of basic grade (Baseline Profile) is realized by integrating the third party H.264 hardware decoding IP core, and the software part completes the video output display. This paper simulates the functions of third-party IP cores based on Modelsim, and then discusses the process of integrating custom IP cores in XPS in detail, including the realization of PLB interface, the establishment of IP core directory and the debugging of IP cores by Chip Scope. The experiment results show that the IP core can be decoded by the third party hardware, and the H.264 video can be decoded in real time with the basic QCIF size. In addition, this paper presents a hardware architecture of H.264 decoder combined with hardware and software. The design of CAVLC entropy decoding sub-module is completed with Verilog language. The simulation results on Modelsim show that the module functions correctly.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.81

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