可配置双路脉冲压缩的设计与实现
发布时间：2018-10-29 23:02
【摘要】：脉冲压缩技术被广泛的应用在现代雷达系统中,可以同时确保雷达的作用距离以及距离分辨力。而当今雷达已由模拟化转向数字化,大大提升了雷达信号处理器的处理速度以及可靠性等方面。目前对于脉冲压缩处理的实现方法有FPGA,DSP和ASIC。但由于采用DSP和FPGA来实现时,其不但成本较高,并且难以满足现代雷达信号处理的实时性要求。随着当代集成电路的发展,单个芯片的处理能力得到了提升,因而采用ASIC的实现方式可以满足雷达信号处理的实时性,同时易于批量化的生产可以降低成本。因此,采用ASIC的实现方式是有必要的。本文基于雷达信号处理的理论知识,主要研究了脉冲压缩技术的ASIC实现方式。首先对雷达信号以及脉冲压缩的算法进行了研究,并确定采用频域的处理方法;其次根据设计目标,设计了基于SDF结构的32~4096点可变点流水线型FFT处理器的硬件电路结构,同时对相关电路进行了优化,并且基于上述FFT处理器的结构提出了双输入模式的FFT处理器结构;然后提出了可配置的双路脉冲压缩的方法,此方法增加了应用的灵活性以及减小了面积的开销;最后完成了这两部分的ASIC前端设计以及在功能和时序上的验证工作。本论文采用Matlab搭建验证平台,分别进行了FFT处理器的功能验证以及脉冲压缩电路的功能验证,同时对其结果进行了误差分析,结果显示FFT处理器的相对误差仅为10-5左右,并且脉冲压缩电路的功能正确。对于上述的设计,同时采用综合工具Design Compiler#174;,在SMIC.13的标准工艺库下,完成了脉冲压缩电路的逻辑综合,采用Formality#174;进行形式验证,并且通过PrimeTime#174;对其网表进行了时序分析。
[Abstract]:Pulse compression technology is widely used in modern radar systems, which can ensure the range and range resolution of radar simultaneously. Today, radar has changed from analog to digital, which greatly improves the processing speed and reliability of radar signal processor. At present, the methods of pulse compression are FPGA,DSP and ASIC.. However, when DSP and FPGA are used to realize it, it is not only costly, but also difficult to meet the real-time requirement of modern radar signal processing. With the development of modern integrated circuits, the processing capability of a single chip has been improved. Therefore, the implementation of ASIC can meet the real-time performance of radar signal processing, and easy batch production can reduce the cost. Therefore, it is necessary to implement ASIC. Based on the theoretical knowledge of radar signal processing, this paper mainly studies the ASIC implementation of pulse compression technology. Firstly, the algorithms of radar signal and pulse compression are studied, and the frequency domain processing method is determined. Secondly, according to the design goal, the hardware circuit structure of the 32 / 4096 point variable point pipelined FFT processor based on SDF structure is designed, and the related circuits are optimized. Based on the structure of the FFT processor, a dual-input mode FFT processor architecture is proposed. Then, a configurable dual-channel pulse compression method is proposed, which increases the flexibility of the application and reduces the area overhead. Finally, the design of the ASIC front-end and the verification of the function and timing of the two parts are completed. In this paper, Matlab is used to build the verification platform, the function verification of FFT processor and the function verification of pulse compression circuit are carried out, and the error analysis of the result shows that the relative error of FFT processor is only about 10-5. And the function of pulse compression circuit is correct. For the above design, the logic synthesis of the pulse compression circuit is completed by using the synthesis tool Design Compiler#174;, under the standard process library of SMIC.13. The logic synthesis of the pulse compression circuit is verified by Formality#174; and verified by PrimeTime#174;. The network table is analyzed in time series.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.51
本文编号：2299090
[Abstract]:Pulse compression technology is widely used in modern radar systems, which can ensure the range and range resolution of radar simultaneously. Today, radar has changed from analog to digital, which greatly improves the processing speed and reliability of radar signal processor. At present, the methods of pulse compression are FPGA,DSP and ASIC.. However, when DSP and FPGA are used to realize it, it is not only costly, but also difficult to meet the real-time requirement of modern radar signal processing. With the development of modern integrated circuits, the processing capability of a single chip has been improved. Therefore, the implementation of ASIC can meet the real-time performance of radar signal processing, and easy batch production can reduce the cost. Therefore, it is necessary to implement ASIC. Based on the theoretical knowledge of radar signal processing, this paper mainly studies the ASIC implementation of pulse compression technology. Firstly, the algorithms of radar signal and pulse compression are studied, and the frequency domain processing method is determined. Secondly, according to the design goal, the hardware circuit structure of the 32 / 4096 point variable point pipelined FFT processor based on SDF structure is designed, and the related circuits are optimized. Based on the structure of the FFT processor, a dual-input mode FFT processor architecture is proposed. Then, a configurable dual-channel pulse compression method is proposed, which increases the flexibility of the application and reduces the area overhead. Finally, the design of the ASIC front-end and the verification of the function and timing of the two parts are completed. In this paper, Matlab is used to build the verification platform, the function verification of FFT processor and the function verification of pulse compression circuit are carried out, and the error analysis of the result shows that the relative error of FFT processor is only about 10-5. And the function of pulse compression circuit is correct. For the above design, the logic synthesis of the pulse compression circuit is completed by using the synthesis tool Design Compiler#174;, under the standard process library of SMIC.13. The logic synthesis of the pulse compression circuit is verified by Formality#174; and verified by PrimeTime#174;. The network table is analyzed in time series.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.51
【参考文献】
相关硕士学位论文 前1条
1 汤海华;雷达信号处理脉冲压缩的设计与实现[D];西安电子科技大学;2014年
，本文编号：2299090
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