基于FPGA的Ku波段雷达信号模拟器控制模块设计与实现

发布时间：2018-11-03 09:26

【摘要】：雷达测试系统,是用来测试雷达系统性能,评估雷达工作状态的系统。雷达测试系统的测试信号源可以产生雷达在各种工作环境下可能接收到的回波信号的精确重现并用模拟回波信号测试雷达各个子系统和整体系统的性能或工作情况,是雷达测试系统的核心。本文详细介绍基于FPGA的Ku波段的雷达测试信号源频综器控制系统研制过程。系统硬件实现采用了6层PCB板设计,仔细考虑了对系统性能有较大影响的电源模块,FPGA配置模块,控制接口等方面的电路设计和实现。频综模块采用Verilog编写控制模块。串口模块运用了嵌入式软核(Microblaze)技术来实现。根据系统从低频时钟域向高频时钟域发送数据的特点,系统采用了触发器级联和FIFO缓存的方式解决数据跨时钟域传输的同步化问题。系统的时序生成控制部分使用了模块化的设计思路。控制数据和控制功能相互隔离,提高配置数据使用的灵活性。控制模块通过总线的方式连接,由一个总控模块调用各个模式下所需要的系统的各个功能模块,并控制整个系统的工作时序。本文还详细的介绍了系统的测试结果,从时域、频域、调制域以及FPGA产生的控制信号测试了整个系统的功能和性能,系统的性能指标达到了预期的目的。同时,也给出了在系统测试过程中发现的诸多的问题以及解决这些问题的方法,探讨了现阶段还没有实现但可能改善系统性能的一些思路。
[Abstract]:Radar test system is used to test the performance of radar system and evaluate the working state of radar. The test signal source of the radar test system can produce the accurate reproduction of the echo signal which may be received by the radar under various working conditions and test the performance or working condition of each subsystem and the whole system of the radar by simulating the echo signal. It is the core of radar test system. This paper introduces in detail the development of radar test signal source frequency synthesizer control system based on FPGA in Ku band. The six-layer PCB board is used to realize the hardware of the system. The circuit design and implementation of power supply module, FPGA configuration module, control interface and so on, which have great influence on the system performance, are carefully considered. The frequency synthesis module uses Verilog to write the control module. The serial module uses embedded soft core (Microblaze) technology to realize. According to the characteristics of transmitting data from low frequency clock domain to high frequency clock domain, the system adopts trigger cascade and FIFO cache to solve the synchronization problem of data transmission across clock domain. The timing generation control part of the system uses the modular design idea. The control data and control function are isolated from each other, and the flexibility of configuration data is improved. The control module is connected by bus, and each function module of the system is called by a master control module, and the working sequence of the whole system is controlled. This paper also introduces the test results of the system in detail. The function and performance of the system are tested from time domain, frequency domain, modulation domain and control signal generated by FPGA. The performance of the system achieves the desired purpose. At the same time, many problems found in the process of system testing and the methods to solve these problems are also given, and some ideas for improving the system performance are discussed, which have not been realized yet but may be improved at the present stage.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.51

【共引文献】