高速率LDPC编译码器设计与实现

发布时间：2018-11-06 18:41

【摘要】：LDPC码是由它的奇偶校验矩阵完全确定的线性分组码,LDPC码最初是在上世纪60年代由Gallager在他的博士论文中提出,此后很长一段时间由于缺乏可行的高效译码算法,一直被人们忽略。直到1981年Tanner提出了LDPC码的图表表示方法,即后来为人们熟知的Tanner图,LDPC码才重新引起了科学家们的注意。1995年MacKay和Neal等通过自己的不懈研究,提出了性能良好而且易于实现的LDPC译码算法,高性能LDPC码算法探究再次来到了科学研究的前沿。如今,经过十几年的发展,LDPC码的相关技术已经日趋成熟,甚至开始进入了商业化的应用市场,并被写进了无线通信等相关领域的标准之中。随着未来宽带通信的快速发展,传统的LDPC的BP译码算法,LLR BP译码算法,SPA译码算法等传统算法已经无法满足大规模集成电路运算实现快速译码要求,为此,一种基于传统译码算法的高效算法被提出来,这就是我们将概率计算运用到LDPC译码的初衷,它的核心思想是采用随机比特流是连续的值,可以通过简单的按位运算计算复杂的算法,概率计算的一个明显的优势是,概率计算算法的硬件实现比传统的基数算法简单得多,例如,乘法是仅由一个与门操作实现,缩放的结构则是一个多路复用器,硬件的简单性带来了关键路径的缩短以及功耗的降低。此外,在一个随机比特流的所有的位都有相同的意义,这意味着概率计算的算法是一元算法具有比传统算法更好的容错编码性。本文主要是研究了多码率LDPC编译码系统的FPGA实现和概率计算中序列相关性理论推导及实验分析。主要的工作和创新点如下:1.构建LDPC编译码测试平台,主要内容有:完成了LDPC编解码器设计与仿真测试平台的搭建并完成了功能测试;2.概率计算中转换的概率序列相关性研究,主要内容有:研究了概率计算中概率序列相关性对于整体译码性能的影响;3.完成多码率LDPC译码器的FPGA开发流程,主要内容有:利用Virtex6/7系列的475T/485T芯片完成误码率和不同SNR条件下迭代次数DC的下板实测。
[Abstract]:LDPC codes are linear block codes that are completely determined by its parity matrix. LDPC codes were first proposed by Gallager in his doctoral thesis in the 1960s, and for a long time thereafter, due to the lack of feasible efficient decoding algorithms, Has been ignored by people. It was not until 1981, when Tanner put forward a graphic representation of LDPC codes, that is, the Tanner diagrams that were known to many people, that LDPC codes came back to the attention of scientists. In 1995, MacKay and Neal, and so on, made unremitting research through their own studies. A LDPC decoding algorithm with good performance and easy implementation is proposed. The research of high performance LDPC code algorithm comes to the forefront of scientific research again. Now, with the development of more than ten years, the related technology of LDPC code has matured day by day, and even entered the commercial application market, and has been written into the wireless communication and other related field standards. With the rapid development of broadband communication in the future, the traditional BP decoding algorithm of LDPC, LLR BP decoding algorithm, SPA decoding algorithm and other traditional algorithms can no longer meet the requirement of fast decoding for large scale integrated circuit operation. An efficient algorithm based on traditional decoding algorithm has been proposed, which is the original intention of applying probabilistic computation to LDPC decoding. Its core idea is to use random bit streams as continuous values. A simple bit operation can be used to calculate complex algorithms. One obvious advantage of probability calculation is that the hardware implementation of probabilistic algorithms is much simpler than that of traditional cardinality algorithms. For example, multiplication is implemented by only one and gate operation. The architecture of scaling is a multiplexer. The simplicity of hardware results in the shortening of critical paths and the reduction of power consumption. In addition, all bits in a random bit stream have the same meaning, which means that the probabilistic algorithm is a univariate algorithm with better fault-tolerant coding than the traditional algorithm. In this paper, the sequence correlation theory and experimental analysis of the FPGA implementation and probability calculation of multi-rate LDPC codec and decode system are studied. The main work and innovation are as follows: 1. The main contents of this paper are as follows: the design of LDPC codec and simulation test platform are completed and the function test is completed. 2. The correlation of probabilistic sequence transformed in probability calculation is studied. The main contents are as follows: the influence of correlation of probabilistic sequence on the whole decoding performance is studied; 3. The FPGA development process of multi-rate LDPC decoder is completed. The main contents are as follows: using Virtex6/7 series of 475T/485T chips to complete the BER and the bottom board measurement of the number of iterations of DC under different SNR conditions.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22

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