D-Link DVI高速图像编解码系统设计与实现
发布时间：2018-11-12 07:56
【摘要】：随着高清技术和高速摄像等领域的飞速发展,人们已不再满足于现有的图像精细程度和低速的刷新率。更高分辨率,更高刷新率的多媒体信息是人们生活需求的发展趋势,也是科学技术的发展趋势。图像编解码系统作为高速图像处理的核心单元,其编解码能力的好坏,直接影响着多媒体信息的质量与传输效率。目前数字图像处理系统广泛采用DVI1.0标准接口传输数字视频。根据成像系统的需求,本文设计并实现了一套D-Link DVI高速图像编解码系统。该系统以Xilinx Kintex 7 FPGA为核心处理器、以DDR3 SDRAM为存储设备,以DVI, VGA为数据传输接口,解决了成像系统受限于最高像素时钟只能达到165MHz,无法传输更高帧频、更高分辨率数字图像的问题。该系统内部利用流水线设计思想、查表法、乒乓操作以及MCB控制核实现了DVI双通道的接收与发送,视频图像实时编码算法处理,视频图像降帧处理和DVI至VGA视频信号的转换等功能。本文在介绍视频传输接口规范、核心处理器及存储器原理的基础上,详细叙述了系统组成、双链路DVI设计方案、系统关键技术、硬件电路板制作、编解码算法逻辑实现和系统整体调试分析。该系统最大像素时钟可达330MHz。
[Abstract]:With the rapid development of high-definition technology and high-speed video, people are no longer satisfied with the existing image fine degree and low speed refresh rate. The multimedia information with higher resolution and higher refresh rate is the development trend of people's living needs, and also the development trend of science and technology. As the core unit of high-speed image processing, image coding and decoding system has a direct impact on the quality and transmission efficiency of multimedia information. At present, DVI1.0 standard interface is widely used in digital image processing system to transmit digital video. According to the requirement of imaging system, this paper designs and implements a D-Link DVI high-speed image coding and decoding system. The system uses Xilinx Kintex 7 FPGA as the core processor, DDR3 SDRAM as the storage device and DVI, VGA as the data transmission interface. The system solves the problem that the maximum pixel clock can only reach 165 MHz, which can not transmit higher frame rate. The problem of higher resolution digital images. The system uses pipeline design idea, table searching method, ping-pong operation and MCB control core to realize the receiving and transmitting of DVI dual channels, and real-time video image coding algorithm processing. Video image frame reduction processing and DVI to VGA video signal conversion and other functions. Based on the introduction of video transmission interface specification, core processor and memory principle, this paper describes in detail the composition of the system, the design scheme of dual-link DVI, the key technology of the system, and the fabrication of hardware circuit board. The logic realization of codec algorithm and the whole debugging analysis of the system. The maximum pixel clock of the system can reach 330 MHz.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.81
本文编号：2326531
[Abstract]:With the rapid development of high-definition technology and high-speed video, people are no longer satisfied with the existing image fine degree and low speed refresh rate. The multimedia information with higher resolution and higher refresh rate is the development trend of people's living needs, and also the development trend of science and technology. As the core unit of high-speed image processing, image coding and decoding system has a direct impact on the quality and transmission efficiency of multimedia information. At present, DVI1.0 standard interface is widely used in digital image processing system to transmit digital video. According to the requirement of imaging system, this paper designs and implements a D-Link DVI high-speed image coding and decoding system. The system uses Xilinx Kintex 7 FPGA as the core processor, DDR3 SDRAM as the storage device and DVI, VGA as the data transmission interface. The system solves the problem that the maximum pixel clock can only reach 165 MHz, which can not transmit higher frame rate. The problem of higher resolution digital images. The system uses pipeline design idea, table searching method, ping-pong operation and MCB control core to realize the receiving and transmitting of DVI dual channels, and real-time video image coding algorithm processing. Video image frame reduction processing and DVI to VGA video signal conversion and other functions. Based on the introduction of video transmission interface specification, core processor and memory principle, this paper describes in detail the composition of the system, the design scheme of dual-link DVI, the key technology of the system, and the fabrication of hardware circuit board. The logic realization of codec algorithm and the whole debugging analysis of the system. The maximum pixel clock of the system can reach 330 MHz.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.81
【参考文献】
相关硕士学位论文 前1条
1 黎宝峰;嵌入式DSP处理器的设计与验证[D];湖南大学;2003年
，本文编号：2326531
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