相位噪声测试中数据通道设计与实现

发布时间：2018-11-20 16:19

【摘要】：相位噪声用来说明信号短期频率稳定性和可靠性,是电子测量领域中的重要指标,相位噪声测试在信号分析和测试中有着重要的地位。论文旨在完成相位噪声测试系统中数据通道的设计与实现,为整个相位噪声测试系统提供底层的数据链路支持。文中通过分析相位噪声测试系统的总体结构说明了相位噪声测试系统的数据通道组成,包括将系统前端采集到的模拟信号通过模数转换电路转换后送入数字电路中,FPGA电路对输入的数字信号采用FIFO实现数据缓存,将数字信号通过位宽转换送入DDR3 SDRAM存储器中,当存储器中的所存的数据内容达到预设值时,FPGA电路控制ADC采样,将存储器中的数据通过高速串行接口传输到后级DSP信号处理系统中。本文主要完成的工作有:1.通过对鉴相法相位噪声测试系统总体结构和各部分功能分析,说明了测试系统中数字信号的数据通道组成。2.介绍了双通道模数转换器的配置操作原理和FIFO接口的设计使用,在此基础上采用FPGA自带的FIFO核生成器实现了模数转换电路与FPGA电路的独立时钟位宽转换FIFO缓冲结构的功能仿真。3.介绍了DDR3 SDRAM存储器的发展与工作原理,说明了DDR3 SDRAM控制器接口和控制器指令时序操作原理,采用Xilinx FPGA MIG核生成器生成DDR3 SDRAM控制器并做了功能仿真,在FPGA硬件开发板上对控制器的读写功能进行了验证。4.介绍了高速串行接口的系统组成,在此基础上说明了Xilinx Virtex-6 FPGA GTX收发器的内部结构,通过使用Xilinx FPGA核生成器生成GTX收发器,对GTX收发器接口进行了功能仿真。
[Abstract]:Phase noise, which is used to explain the short term frequency stability and reliability of signals, is an important index in the field of electronic measurement. Phase noise measurement plays an important role in signal analysis and testing. The purpose of this paper is to complete the design and implementation of the data channel in the phase noise testing system, and to provide the underlying data link support for the whole phase noise testing system. By analyzing the overall structure of the phase noise testing system, this paper explains the data channel composition of the phase noise testing system, including the analog signals collected from the front end of the system are converted into the digital circuit by A / D conversion circuit. The FPGA circuit uses FIFO to realize the data cache of the input digital signal, and sends the digital signal into the DDR3 SDRAM memory through bit width conversion. When the stored data content in the memory reaches the preset value, the FPGA circuit controls the ADC sampling. The data in the memory is transmitted to the DSP signal processing system through the high speed serial interface. The main work accomplished in this paper is as follows: 1. Based on the analysis of the overall structure and the functions of the phase noise measurement system, the data channel composition of the digital signal in the test system is explained. 2. 2. This paper introduces the configuration and operation principle of dual channel A / D converter and the design and use of FIFO interface. On this basis, the function simulation of the independent clock bit width conversion FIFO buffer structure of A / D conversion circuit and FPGA circuit is realized by using the FIFO core generator of FPGA. 3. This paper introduces the development and working principle of DDR3 SDRAM memory, explains the interface of DDR3 SDRAM controller and the principle of timing operation of controller instruction, uses Xilinx FPGA MIG core generator to generate DDR3 SDRAM controller and makes functional simulation. The read and write function of the controller is verified on the FPGA hardware development board. 4. This paper introduces the system composition of high speed serial interface, and explains the internal structure of Xilinx Virtex-6 FPGA GTX transceiver. By using Xilinx FPGA core generator to generate GTX transceiver, the function of GTX transceiver interface is simulated.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.4

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