60GHz频段下单载波链路的基带电路设计与实现
发布时间：2018-12-14 03:19
【摘要】：随着高速无线互联应用场景的增加,人们对短距离通信技术的传输速率要求越来越高,现有的处于低频段的WiFi技术很难满足千兆传输速率,因此具有高达7GHz免授权频谱的60GHz毫米波频段日益引起了大家的关注。在接收端,射频RF和基带是两个重要的组成部分,其中60GHz射频技术已经获得了较好解决而高速低功耗的60GHz基带技术依然是一个挑战。本文参照IEEE802.11ad标准,探讨了单载波调制下的60GHz接收机基带算法及部分FPGA实现,同时针对高速时间交叉采样ADC的接口设计和测试也做了一些研究和设计。第一章概述了60GHz的研究背景和研究现状。分析了60GHz频段的特点并给出了本文的架构安排。第二章首先从大尺度衰落和小尺度衰落两方面简单介绍了60GHz的信道,给出了本设计仿真用的信道参数,其次简单介绍了IEEE802.11ad的物理层帧结构,同时还介绍了在60GHz基带中起重要作用的Golay互补序列的相关背景、生成算法和相关器设计。最后介绍了时间交叉采样ADC的工作原理和模型,并分析了直流偏移、增益失配、时钟相位失配这三种情况对ADC性能的影响第三章首先给出了一个基于FPGA实现平台的60GHz基带的总框架图,确定ADC采样速率和FPGA内部电路并行数。接着描述了数据分组和去?2旋转的两个小模块。然后针对帧检测、载波频偏同步、信道估计算法、采样定时同步和均衡算法做了探索和仿真。第四章首先对本设计中60GHz硬件平台中进行阐述,并对采样率达3.52Gsample/s高速时间交叉ADC进行研究,主要包括ADC与FPGA接口设计、通道失配校正、ADC参数测试提取。同时介绍了高速并行Golay序列相关器的FPGA实现方案和测试结果,最后针对60GHz高速并行的传输特点,设计了特殊的NCO,比常规的并行NCO节省了87.5%的面积。最后一章总结了本文的工作,给出了结论,以及下一步要进行的主要工作。
[Abstract]:With the increase of high speed wireless interconnection applications, the transmission rate of short distance communication technology is becoming more and more high. The existing WiFi technology in low frequency band is difficult to meet the gigabit transmission rate. Therefore, 60GHz millimeter wave band with up to 7GHz-free spectrum has attracted more and more attention. In the receiver, RF and baseband are two important components. Among them, 60GHz RF technology has been solved well, but the 60GHz baseband technology with high speed and low power consumption is still a challenge. Referring to the IEEE802.11ad standard, this paper discusses the baseband algorithm and partial FPGA implementation of 60GHz receiver under single carrier modulation. At the same time, the interface design and test of high speed time cross-sampling ADC are also studied and designed. The first chapter summarizes the research background and research status of 60GHz. The characteristics of 60GHz band are analyzed and the architecture of this paper is given. In the second chapter, the channel of 60GHz is introduced from two aspects: large scale fading and small scale fading, and the channel parameters used in the design and simulation are given. Secondly, the physical layer frame structure of IEEE802.11ad is briefly introduced. At the same time, the background, generation algorithm and correlator design of Golay complementary sequences which play an important role in 60GHz baseband are also introduced. Finally, the working principle and model of time cross sampling ADC are introduced, and the DC offset and gain mismatch are analyzed. The influence of clock Phase mismatch on ADC performance Chapter 3 first gives a general frame diagram of the 60GHz baseband based on the FPGA implementation platform and determines the ADC sampling rate and the parallel number of FPGA internal circuits. Then it describes two small modules of data grouping and de-2 rotation. Then, the frame detection, carrier frequency offset synchronization, channel estimation algorithm, sampling timing synchronization and equalization algorithm are explored and simulated. In the fourth chapter, the 60GHz hardware platform is introduced, and the sampling rate of 3.52Gsample/s high speed time crossover ADC is studied, including the design of ADC and FPGA interface, channel mismatch correction, ADC parameter test and extraction. At the same time, the FPGA implementation scheme and test results of high speed parallel Golay sequence correlator are introduced. Finally, according to the characteristics of 60GHz high speed parallel transmission, the special NCO, is designed to save 87.5% area compared with the conventional parallel NCO. The last chapter summarizes the work of this paper, gives the conclusion, and the main work to be done next.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN928
[Abstract]:With the increase of high speed wireless interconnection applications, the transmission rate of short distance communication technology is becoming more and more high. The existing WiFi technology in low frequency band is difficult to meet the gigabit transmission rate. Therefore, 60GHz millimeter wave band with up to 7GHz-free spectrum has attracted more and more attention. In the receiver, RF and baseband are two important components. Among them, 60GHz RF technology has been solved well, but the 60GHz baseband technology with high speed and low power consumption is still a challenge. Referring to the IEEE802.11ad standard, this paper discusses the baseband algorithm and partial FPGA implementation of 60GHz receiver under single carrier modulation. At the same time, the interface design and test of high speed time cross-sampling ADC are also studied and designed. The first chapter summarizes the research background and research status of 60GHz. The characteristics of 60GHz band are analyzed and the architecture of this paper is given. In the second chapter, the channel of 60GHz is introduced from two aspects: large scale fading and small scale fading, and the channel parameters used in the design and simulation are given. Secondly, the physical layer frame structure of IEEE802.11ad is briefly introduced. At the same time, the background, generation algorithm and correlator design of Golay complementary sequences which play an important role in 60GHz baseband are also introduced. Finally, the working principle and model of time cross sampling ADC are introduced, and the DC offset and gain mismatch are analyzed. The influence of clock Phase mismatch on ADC performance Chapter 3 first gives a general frame diagram of the 60GHz baseband based on the FPGA implementation platform and determines the ADC sampling rate and the parallel number of FPGA internal circuits. Then it describes two small modules of data grouping and de-2 rotation. Then, the frame detection, carrier frequency offset synchronization, channel estimation algorithm, sampling timing synchronization and equalization algorithm are explored and simulated. In the fourth chapter, the 60GHz hardware platform is introduced, and the sampling rate of 3.52Gsample/s high speed time crossover ADC is studied, including the design of ADC and FPGA interface, channel mismatch correction, ADC parameter test and extraction. At the same time, the FPGA implementation scheme and test results of high speed parallel Golay sequence correlator are introduced. Finally, according to the characteristics of 60GHz high speed parallel transmission, the special NCO, is designed to save 87.5% area compared with the conventional parallel NCO. The last chapter summarizes the work of this paper, gives the conclusion, and the main work to be done next.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN928
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