基于FPGA的单片SDRAM视频读写乒乓操作设计与优化
发布时间：2018-12-14 19:29
【摘要】：在工业生产中,很多控制设备利用液晶显示屏显示设备当前状态,当外部干扰使数据发送时钟错误或者数据的采集与显示速度不同,显示屏会产生画面偏移或者迟钝的现象。针对该问题,本文提出一种基于FPGA的单片SDRAM的视频缓存控制,在研究SDRAM的结构基础上,编写Verilog语言实现单片SDRAM的乒乓读写操作,利用读写时差和SDRAM的BANK切换存储,使用FIFO实现异步时钟的数据交换,提高数据吞吐量,当数据时钟受干扰时能自动刷新。本文对更功能模块进行分析,根据设计要求选择合适的FPGA和SDRAM芯片,并根据芯片设计制作PCB电路板,搭建硬件调试平台,利用一个800×480像素LCD液晶显示屏显示画面,画面稳定流畅。
[Abstract]:In industrial production, many control devices use liquid crystal display screen to display the current state of the device. When the external interference makes the data send clock error or the data acquisition and display speed is different, the display screen will produce the phenomenon of picture offset or dullness. To solve this problem, this paper proposes a video buffer control based on FPGA for monolithic SDRAM. On the basis of studying the structure of SDRAM, we write the Verilog language to realize the ping-pong reading and writing operation of single SDRAM, and use the time difference of reading and writing and BANK of SDRAM to switch storage. FIFO is used to realize the data exchange of asynchronous clock to improve the data throughput and refresh automatically when the data clock is disturbed. In this paper, the more functional modules are analyzed, the appropriate FPGA and SDRAM chips are selected according to the design requirements, and the PCB circuit board is designed according to the design of the chip. The hardware debugging platform is built, and a 800 脳 480 pixel LCD screen is used to display the screen. The picture is stable and smooth.
【作者单位】： 五邑大学信息工程学院;
【分类号】：TN873.93
，
本文编号：2379191
[Abstract]:In industrial production, many control devices use liquid crystal display screen to display the current state of the device. When the external interference makes the data send clock error or the data acquisition and display speed is different, the display screen will produce the phenomenon of picture offset or dullness. To solve this problem, this paper proposes a video buffer control based on FPGA for monolithic SDRAM. On the basis of studying the structure of SDRAM, we write the Verilog language to realize the ping-pong reading and writing operation of single SDRAM, and use the time difference of reading and writing and BANK of SDRAM to switch storage. FIFO is used to realize the data exchange of asynchronous clock to improve the data throughput and refresh automatically when the data clock is disturbed. In this paper, the more functional modules are analyzed, the appropriate FPGA and SDRAM chips are selected according to the design requirements, and the PCB circuit board is designed according to the design of the chip. The hardware debugging platform is built, and a 800 脳 480 pixel LCD screen is used to display the screen. The picture is stable and smooth.
【作者单位】： 五邑大学信息工程学院;
【分类号】：TN873.93
，
本文编号：2379191
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