基于2.4GHz的数字基带系统设计与实现

发布时间：2018-12-15 00:59

【摘要】：随着国内城市交通的快速发展,高速公路的修建数目和覆盖面积不断增加。目前国内几大城市纷纷将智能收费系统的建设提上日程。本文致力于智能收费系统中的数字基带系统的研究工作,设计并实现一种兼容ZigBee和蓝牙协议的数字基带系统。本论文首先设计了2.4GHz数字基带系统的架构,该架构包括模拟前端、数字基带、寄存器、协议处理和I/O等模块,其中,数字基带模块由发送子系统和接收子系统构成。基于该架构,使用Verilog HDL(hardware description language,硬件描述语言)设计了数字基带发送子系统,该发送子系统由PPDU、symbol-to-chip、chip-to-precode、CRC和白化五个模块组成,采用symbol-to-chip和chip-to-precode技术完成码元的变化和频率调制,实现了ZigBee协议与蓝牙协议的兼容,仿真结果表明发送模块采用16MHz的时钟频率时,每秒发送2M比特的数据;使用Verilog HDL硬件描述语言设计了数字基带接收子系统,该接收子系统包含下变频、低通滤波、微分解调、包检测、帧同步和帧解析六个模块。其中,解调由下变频、低通滤波和微分解调等三个模块实现并完成了时钟频率从32MHz到16MHz的切换,解码由包检测、帧同步和帧解析等三个模块实现并完成了数据的存储,仿真结果表明下变频后采用16MHz的时钟频率,每秒能够接收2M比特的数据。最后,在数字基带系统实现的基础上,采用Synopsys公司的VCS工具进行了系统功能的仿真验证,仿真结果表明,该系统实现了兼容ZigBee协议和蓝牙协议的发送和接收功能,并且当系统采用16MHz的时钟频率时,每秒处理的数据流可达2Mbit,达到了设计要求。为短距离无线通信系统的研究奠定了基础,具有一定的参考价值。
[Abstract]:With the rapid development of urban traffic in China, the number of expressway construction and the coverage area are increasing. At present, the construction of intelligent charging system has been put on the agenda in several domestic cities. This paper is devoted to the research of digital baseband system in intelligent toll collection system, and designs and implements a digital baseband system compatible with ZigBee and Bluetooth protocol. This paper first designs the architecture of 2.4GHz digital baseband system, which includes analog front end, digital baseband, register, protocol processing and I / O modules. The digital baseband module is composed of sending subsystem and receiving subsystem. Based on this architecture, a digital baseband transmission subsystem is designed by using Verilog HDL (hardware description language, hardware description language. The subsystem is composed of five modules, PPDU,symbol-to-chip,chip-to-precode,CRC and whitening. Using symbol-to-chip and chip-to-precode technology to complete symbol change and frequency modulation, the compatibility of ZigBee protocol and Bluetooth protocol is realized. The simulation results show that the transmitting module transmits 2 megabits of data per second using the clock frequency of 16MHz. A digital baseband receiving subsystem is designed by using Verilog HDL hardware description language. The subsystem consists of six modules: downconversion, low-pass filtering, differential demodulation, packet detection, frame synchronization and frame analysis. Among them, demodulation is realized by downconversion, low-pass filtering and differential demodulation, and clock frequency switching from 32MHz to 16MHz is completed. Decoding is realized by packet detection, frame synchronization and frame analysis, and data storage is completed. The simulation results show that the 16MHz clock frequency can receive 2 megabits of data per second. Finally, based on the realization of the digital baseband system, the system function is simulated and verified by the VCS tool of Synopsys Company. The simulation results show that the system realizes the functions of sending and receiving compatible ZigBee protocol and Bluetooth protocol. And when the clock frequency of 16MHz is adopted, the data stream per second can reach 2 Mbit, which meets the design requirements. It lays a foundation for the research of short-range wireless communication system and has certain reference value.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN92

【相似文献】