基于多核DSP的通用软件无线电平台设计与实现
发布时间：2019-01-23 12:21
【摘要】：随着通信技术特别是无线通信技术的飞速发展,各种不同通信标准和协议被应用于无线通讯领域。同时,基于人们对无线通信领域中低时延、高吞吐率数据传输的需求,使得传输标准和协议的更新换代变得越来越频繁,无线通信系统的实现也变得越来越复杂。为适应这些变化,设计并实现一个标准通用的软件无线电平台显得十分重要。 本文从硬件实现、接口互联标准和系统软件架构三个角度出发,对比和分析了现有通用软件无线电平台的实现方案,并在此基础上提出了一种基于多核DSP的通用软件无线电系统平台设计方案。本文研究了当前处理器的多核技术,详细介绍了KeyStone架构下多核处理的相关软硬件实现细节。 针对多核DSP的通用软件无线电系统平台设计方案,本文从硬件和软件两个方面着手,详细介绍了基于Virtex-6系列FPGA的多通道模拟信号采集前端和多核DSP数字信号处理后端的具体设计细节。阐述并实现了基于RapidIO串行协议的高速互联技术。 针对硬件电路板设计部分,本文从高速PCB设计角度出发,详细介绍了多层电路板叠层设计、电源平面分割、拓扑结构选择和等长走线约束设置等内容。给出了高速ADC采样芯片、DDR3存储芯片相关的约束设置细节和走线实际延时参数。
[Abstract]:With the rapid development of communication technology, especially wireless communication technology, various communication standards and protocols have been applied in wireless communication field. At the same time, due to the demand of low delay and high throughput data transmission in wireless communication field, the updating of transmission standards and protocols becomes more and more frequent, and the implementation of wireless communication system becomes more and more complex. In order to adapt to these changes, it is very important to design and implement a standard general software radio platform. From three aspects of hardware implementation, interface interconnection standard and system software architecture, this paper compares and analyzes the implementation schemes of the existing general software radio platform. On this basis, a general software radio system platform based on multi-core DSP is proposed. In this paper, the current multi-core processor is studied, and the hardware and software implementation details of multi-core processing based on KeyStone architecture are introduced in detail. Aiming at the general software radio system platform design of multi-core DSP, this paper starts from two aspects: hardware and software. The design details of multi-channel analog signal acquisition front end and multi-core DSP digital signal processing back-end based on Virtex-6 series FPGA are introduced in detail. The technology of high speed interconnection based on RapidIO serial protocol is described and realized. Aiming at the design of hardware circuit board, this paper introduces in detail the design of multilayer circuit board, power plane partition, topology selection and constraint setting of equal length running line from the point of view of high speed PCB design. The high speed ADC sampling chip, the constraint setting details of DDR3 memory chip and the actual delay parameters are given.
【学位授予单位】：南京理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN925
本文编号：2413765
[Abstract]:With the rapid development of communication technology, especially wireless communication technology, various communication standards and protocols have been applied in wireless communication field. At the same time, due to the demand of low delay and high throughput data transmission in wireless communication field, the updating of transmission standards and protocols becomes more and more frequent, and the implementation of wireless communication system becomes more and more complex. In order to adapt to these changes, it is very important to design and implement a standard general software radio platform. From three aspects of hardware implementation, interface interconnection standard and system software architecture, this paper compares and analyzes the implementation schemes of the existing general software radio platform. On this basis, a general software radio system platform based on multi-core DSP is proposed. In this paper, the current multi-core processor is studied, and the hardware and software implementation details of multi-core processing based on KeyStone architecture are introduced in detail. Aiming at the general software radio system platform design of multi-core DSP, this paper starts from two aspects: hardware and software. The design details of multi-channel analog signal acquisition front end and multi-core DSP digital signal processing back-end based on Virtex-6 series FPGA are introduced in detail. The technology of high speed interconnection based on RapidIO serial protocol is described and realized. Aiming at the design of hardware circuit board, this paper introduces in detail the design of multilayer circuit board, power plane partition, topology selection and constraint setting of equal length running line from the point of view of high speed PCB design. The high speed ADC sampling chip, the constraint setting details of DDR3 memory chip and the actual delay parameters are given.
【学位授予单位】：南京理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN925
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，本文编号：2413765
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