AES算法研究及FPGA实现

发布时间：2019-06-21 04:28

【摘要】：在计算机网络技术蓬勃发展之际，基于计算机网络的应用型服务得到了飞速的发展，互联网信息的安全性引起了研究领域和商业领域的共同关注。尽管目前加密的手段种类繁杂，并且在各行各业中都已经形成了自己的规范体系，但安全问题仍然是信息时代的重要议题。由于网络发展的速度快于数据安全思想，因此在网络被广泛应用的今天，安全问题也愈发突出。大量敏感信息通过计算机网络进行交换，加之网络的开放性，使用户面对信息的安全、高效的传输表示了迫切的需求。AES算法可以很好地解决数据的保密性防护和认证等方面存在的问题。因此对AES算法的安全性问题进行进一步的探索具有重大的研究意义。论文对AES高级密钥算法的理论层和实现层进行了研究。论文首先详细介绍了AES算法的基本原理和现有的有效攻击方法。然后针对AES算法中出现的仿射变换周期过短，迭代输出周期无法充满空间以及正向S盒仿射变换中数学表达式项数过少等问题，提出了基于AES算法中S盒的改进方法。最后提出了基于FPGA的AES加密解密系统设计方案，并通过ISE开发工具自带的ISim软件对系统的加密解密功能进行了仿真验证。论文中提出的S盒改进方法中，采用91组仿射变换对构建基本库，增强了AES算法的抗基于穷举法攻击的能力，另采用二阶段仿射变换将仿射变换周期提高至16，迭代输出周期提高至255，正向S盒变换中S盒仿射变化函数的数学表达式项数提高至255，增强了AES算法的抗基于数学特性攻击的能力。在FPGA设计时，使用Xilinx公司的ISE开发套件，硬件开发板选择的是Xilinx公司的Spartan3ADSP系列，并确定基于AES算法的加密系统设计采用基于迭代的反馈模式。AES加密解密系统的设计包括对字节变换、行变换、列混淆、密钥加和密钥扩展等五个核心模块的设计，，以及对整体控制模块的设计。最终仿真后的数据表明，设计能够完成基于AES算法加密解密的功能，进而证实算法整体的正确性，实现了预期所要求的算法改良目的。
[Abstract]:With the rapid development of computer network technology, the application service based on computer network has been developed rapidly, and the security of Internet information has attracted the common attention of both the research field and the commercial field. Although the types of encryption methods are complex and their own normative systems have been formed in various industries, security is still an important issue in the information age. Because the development of network is faster than the idea of data security, today, when the network is widely used, the security problem is becoming more and more prominent. A large number of sensitive information is exchanged through the computer network, coupled with the openness of the network, which makes users face the security of information and express the urgent need for efficient transmission. AES algorithm can solve the problems existing in the confidentiality protection and authentication of data. Therefore, it is of great significance to further explore the security of AES algorithm. In this paper, the theoretical layer and implementation layer of AES advanced key algorithm are studied. Firstly, the basic principle of AES algorithm and the existing effective attack methods are introduced in detail. Then, an improved method based on AES algorithm is proposed to solve the problems of affine transformation period in AES algorithm, which is too short, the iterative output period can not be filled with space, and the number of mathematical expressions in forward S-box affine transformation is too small. Finally, the design scheme of AES encryption and decryption system based on FPGA is put forward, and the encryption and decryption function of the system is simulated and verified by the ISim software of ISE development tool. In the improved S-box method proposed in this paper, 91 groups of affine transformation pairs are used to construct the basic library, which enhances the ability of AES algorithm to resist the attack based on exhaustive method. In addition, the affine transformation period is increased to 16, the iterative output period is increased to 255, and the number of mathematical expression items of S-box affine change function in forward S-box transformation is increased to 255. the ability of AES algorithm to resist attacks based on mathematical characteristics is enhanced. In the design of FPGA, using the ISE development suite of Xilinx company, the hardware development board selects the Spartan3ADSP series of Xilinx company, and determines that the encryption system based on AES algorithm adopts iterative feedback mode. The design of FPGA encryption and decryption system includes the design of five core modules, such as byte transformation, row transformation, column confusion, key addition and key expansion, as well as the design of the whole control module. The final simulation data show that the design can complete the encryption and decryption function based on AES algorithm, and then verify the correctness of the algorithm as a whole, and achieve the expected purpose of algorithm improvement.
【学位授予单位】：北京工业大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN918.4;TN791

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