基于多核嵌入式HEVC解码器并行优化及实现

发布时间：2017-12-28 04:32

本文关键词：基于多核嵌入式HEVC解码器并行优化及实现　出处：《西南交通大学》2016年硕士论文　论文类型：学位论文

【摘要】：随着移动互联网和多媒体的不断发展,实时高清视频通信越来越受到关注。HEVC为ITU-T(国际电信联盟)和ISO(国际标准化组织)2013年联合推出最新视频编解码标准。由于其压缩率相较于H.264提高50%,网络带宽减少了一半,所以得到广泛关注,但是,HEVC算法复杂度增加,实时编解码对于硬件资源有限的移动设备处理器带来很大压力。由于能耗问题的制约,现在大部分移动设备使用能耗更低ARM架构多核心处理器作为自己CPU,所以,在ARM多核心处理器通过并行计算HEVC提高解码器性能成为一个热点研究问题。首先,本文研究分析了最新HEVC编解码标准相比于H.264的改进之处,总结了解码器的新特性,研究了最新ARM多核架构处理器(Big.LITTLE)体系结构及特性,分析此架构的并行计算特点。然后,分析像素重构(帧内预测、帧间预测、反量化、反变换)过程数据耦合性,研究适合big.LITTLE架构体系处理器并行粒度,本文选用重叠波前并行算法为像素重构实现方案,以CTB行作为基本的并行粒度。其次,研究HEVC解码器过程中环路滤波数据耦合性,分别研究去方块滤波和样点自适应补偿滤波的实现原理。去方块滤波在实现并行化计算时先完成一帧图像的垂直边界滤波,再完成水平行边界滤波,以CTB行和CTB列为并行基本粒度,样点自适应以CTB行或者列为并行基本粒度。为了提高cache命中率和线程在线率,本文的环路滤波并行过程将CTB列的去方块滤波和样点自适应融合为一个并行任务。HEVC解码器经过本文的并行优化设计和实现,对高清(1280×720)和标清(832×480)两种测试序列实现了实时解码,解码帧率相对于串行解码器有了明显提高。
[Abstract]:With the continuous development of mobile Internet and multimedia, real-time high-definition video communication has attracted more and more attention. HEVC jointly launched the latest video coding and decoding standard for ITU-T (International Telecommunication Union) and ISO (International Standardization Organization) in 2013. Because its compression rate is increased by 50% compared with H.264, and the network bandwidth has been reduced by half, it has attracted wide attention. However, the complexity of HEVC algorithm increases, and real-time codec brings great pressure to the mobile device processors with limited hardware resources. Due to the restriction of energy consumption, most of the mobile devices consume less energy than the ARM architecture, and the multi-core processors of the CPU architecture are their own ARM. Therefore, it becomes a hot research topic to improve the decoder performance of ARM multi-core processors through parallel computing. First of all, this paper studies and analyzes the improvement of the latest HEVC encoding and decoding standard compared with H.264, summarizes the new characteristics of the decoder, studies the architecture and characteristics of the latest ARM multi-core architecture processor (Big.LITTLE), and analyzes the parallel computing characteristics of the architecture. Then, analysis of the reconstructed pixels (intra prediction, inter prediction, inverse quantization, inverse transform) process data coupling, research for the big.LITTLE architecture processor parallel granularity parallel algorithm using overlapping wavefront scheme for pixel reconstruction, using CTB as basic parallel granularity. Secondly, the coupling of the loop filter data in the HEVC decoder is studied, and the principle of the block filtering and the adaptive compensation filter is studied respectively. To achieve parallel computing, we first finish the vertical boundary filtering of a single image, and then perform the horizontal row boundary filtering. We use CTB row and CTB column as parallel basic granularity, and sample points are adaptive to row CTB or row as parallel basic granularity. In order to improve cache hit rate and thread online rate, the loop filtering parallel process in this paper integrates CTB block filter and sample adaptation into a parallel task. The HEVC decoder is designed and implemented through parallel optimization in this paper. It achieves real-time decoding for HD (1280 * 720) and standard (832 * 480) two test sequences, and the decoding frame rate has been significantly improved compared with the serial decoder.
【学位授予单位】：西南交通大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN919.81

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