高效低功耗低并行度LDPC编码方法

发布时间：2017-12-31 07:32

本文关键词：高效低功耗低并行度LDPC编码方法　出处：《电子与信息学报》2016年09期 　论文类型：期刊论文

【摘要】：低密度奇偶校验码(LDPC)是最接近香农极限的纠错码之一,具有优良的性能且被国际通信标准组织广泛采纳为信道编码。CCSDS推荐使用LDPC码作为近地空间和深空探测的信道编码方案。该文提出高效,低功耗,低并行度的LDPC编码方法。该方法通过采用插"0"和改变循环矩阵的结构实现了对CCSDS标准中推荐的校验矩阵子矩阵大小为奇数的LDPC码的低并行度编码。通过分析编码过程,提出了只对输入信息中的"1"有效信息位进行编码的方案,减少了编码中移位寄存器的移位次数,大幅度地降低了编码器功耗。文中采用FPGA实现了(8176,7154)78LDPC码的编码器,结果显示在硬件开销略有增加的情况下,编码功耗大幅度下降,编码速率接近低并行度编码方案。
[Abstract]:Low density parity check code (LDPC) is one of the most close to Shannon limit error correction code. It has excellent performance and has been widely adopted by the International Organization of Communication Standards for channel coding. CCSDS recommends the use of LDPC code as a channel coding scheme for near-Earth space and deep space exploration. In this paper, an efficient channel coding scheme is proposed. Low power consumption. LDPC coding method with low parallelism. This method is based on interpolation "0". And changing the structure of cyclic matrix to realize the low parallelism coding of LDPC codes with odd size of check matrix submatrix recommended in CCSDS standard. This paper presents a scheme of encoding only the "1" effective information bits in the input information, which reduces the shift times of the shift registers in the coding. The power consumption of the encoder is greatly reduced. In this paper, the encoder of the code is realized by FPGA, and the result shows that the hardware cost is slightly increased. The coding power consumption is greatly reduced and the coding rate is close to that of the low parallelism coding scheme.
【作者单位】：中国科学院国家空间科学中心;中国科学院复杂航天系统综合电子与信息技术重点实验室;
【分类号】：TN911.22
【正文快照】： 1引言1962年,MIT的GALLAGER首次提出了低密度奇偶校验码[1](LDPC码),但是受限于编译码算法的复杂性和当时的集成电路制造水平,GALLAGER博士的发现没有引起人们的重视。直到1993年,法国学者BERROU等人[2]提出了具有接近Shannon极限的Turbo码之后。剑桥大学的MACKAY等人[3]重新

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