基于FPGA和DDR的高效率矩阵转置方法

发布时间：2018-01-04 17:41

本文关键词：基于FPGA和DDR的高效率矩阵转置方法　出处：《现代雷达》2017年04期 　论文类型：期刊论文

【摘要】：用可编程门阵列(FPGA)作为主处理芯片实现雷达信号处理时,大阶数矩阵转置经常由于双倍速率同步动态随机存储器(DDR)的跳行访问速率而成为系统处理速率的瓶颈。文中分析了DDR的读写机制,对DDR读写时间的组成进行了定量分析,提出了一种提高矩阵转置效率的分块式矩阵转置方法。该方法采用矩阵分块技术,使矩阵转置时DDR的读写速率得以均衡,从而提高DDR读写的平均效率。文中提供了矩阵转置效率的实验室实测数据,验证了该方法的有效性。该方法已在工程实践中得到了成功的应用。
[Abstract]:Using programmable gate array (FPGA) as the main processing chip to realize radar signal processing. High-order matrix transpose is often the bottleneck of system processing rate due to the hopping access rate of double rate synchronous dynamic random access memory (DDR). The mechanism of reading and writing of DDR is analyzed in this paper. The composition of DDR reading and writing time is quantitatively analyzed, and a block matrix transposing method is proposed to improve the efficiency of matrix transposition. The reading and writing rate of DDR can be balanced when matrix transposing, and the average efficiency of DDR reading and writing can be improved. The laboratory measured data of matrix transpose efficiency are provided in this paper. The validity of the method has been verified and the method has been successfully applied in engineering practice.
【作者单位】：南京电子技术研究所;
【分类号】：TN791;TN957.51
【正文快照】： 0引言雷达信号处理的实时性使其对系统的处理速度有着严格的要求[1-2]。近年来,随着处理规模的增加,而中央处理器(CPU)主频难以进一步提升,无法再满足雷达信号处理的高速要求。因此,以大规模可编程门阵列(FPGA)代替CPU作为雷达信号处理的主处理芯片,成为一种新兴的解决方案[3-

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