基于小数N分频的电荷泵锁相环研究与设计

发布时间：2018-02-05 01:53

本文关键词： 电荷泵锁相环小数分频器正交环形振荡器 Σ-Δ调制器　出处：《深圳大学》2017年硕士论文　论文类型：学位论文

【摘要】：基于锁相环的频率合成器被广泛应用于国民生活和军事领域中,如计算机、雷达、通讯、空间勘探、航天、航海等。此外,锁相环还可以用于产生无线通信中的本地振荡信号;可以从接收机的调制信号中恢复基带数据;可以灵活作为调制器适用于不同的调制和解调电路。由于数模混合电路当今发展趋势劲头迅猛,混合型锁相环的结构越来越多样化,综合性能也越来越强。传统的整数型锁相环输出频率的解析度较低,无法满足一些高解析度的系统要求,而小数型锁相环正好能够在晶振频率足够高的情况下实现较高的输出解析度。虽然全数字锁相环的设计具有灵活性和可移植性,但是在对系统需求高的主流电路应用里很多还是使用数模混合锁相环。本文使用数模混合的电路设计流程,设计了一款宽带小数N分频的电荷泵锁相环。本文主要工作以及创新点具体体现在于以下四点:1)基于SP-MASH技术的Σ-Δ调制器。本文设计了一款输入小数位宽为12bit,后级累加器位宽为20bit的SP-MASH小数调制器。该SP-MASH小数调制器同时综合了MASH结构和HK-MASH结构的优点,既有HK-MASH结构相媲美的输出序列周期长度,又保证了如MASH的线性输入,同时也避免从输入引入噪声,极大减少Σ-Δ调制器对锁相环相位噪声的影响。仿真结果表明本文所设计SP-MASH结构Σ-Δ调制器具有优秀的噪声整形特性。在50MHz的时钟下输出底噪小于-200dB,输出周期序列长度最大值为242。2)高电源噪声抑制比的正交多路环形振荡器(QVCO)。该QVCO的最大特点是频率在一定范围内对电源变化不敏感,可以不使用LDO或者其他电源管理技术提高VCO的抗电源噪声能力。通过仿真得到其归一化电源灵敏度最小值为-46dB。VCO使用了压控电阻的调谐手段,本文所设计的VCO的输出频率调谐范围为440MHz-5.18GHz,输出5GHz时的相位噪声为-93dBc/Hz@1MHz。3)高速TSPC 4/5双模预分频器。该预分频器采用伪2/3分频器结构,减少了关键路径上的延迟进而极大提高了最大工作频率,其可工作在4MHz~5.5GHz内。在相同工艺下最高工作频率比传统结构高40%。4)基于调节式共源共栅(Regulated Cascode,RGC)技术的双电荷泵环路结构。调节式共源共栅技术极大提高了电荷泵输出动态范围,在0.2-1.6V控制电压内其电流失配小于0.6%。锁相环环路中采用了双电荷泵结构,与传统单电荷泵结构相比极大地减少了锁定时间。本文采用SMIC 0.18umCMOS工艺设计了一款宽带小数N分频的电荷泵锁相环,其输出频率范围为1.5GHz-4.5GHz,步进约为12KHz。电路仿真表明CPPLL输出频率为4.5GHz时,相位噪声为-94.36dBc/Hz@1MHz,在1.8V电源电压下消耗最大电流为25.8mA,PLL输出锁定时间低于8us。本次设计的锁相环在同类型结构PLL中输出频率范围和锁定时间都有一定的优势。
[Abstract]:The frequency synthesizer based on PLL is widely used in Yu Guomin's life and military fields, such as computer, radar, communication, space exploration, spaceflight, navigation and so on. The PLL can also be used to generate local oscillation signals in wireless communication. Baseband data can be recovered from the modulated signal of the receiver; It can be flexibly used as modulator for different modulation and demodulation circuits. Due to the rapid development trend of digital-analog hybrid circuits, the structure of hybrid PLL is becoming more and more diverse. The traditional integer PLL has lower resolution of output frequency and can not meet some system requirements of high resolution. The decimal PLL can achieve high output resolution at high enough crystal frequency, although the design of all-digital PLL is flexible and portable. However, in the mainstream circuit applications with high demand for the system, a lot of digital-analog hybrid phase-locked loops are used. In this paper, the digital-analog hybrid circuit design process is used. A charge pump phase-locked loop (CPPLL) with wide band fractional N frequency division is designed. The main work and innovation of this paper are as follows: 1). 危-螖 modulator based on SP-MASH technology. A 12bit width input decimal is designed in this paper. SP-MASH decimal modulator with 20 bit bit width of the latter accumulator. The SP-MASH decimal modulator combines the advantages of both the MASH structure and the HK-MASH structure. Not only the output sequence cycle length of HK-MASH structure is comparable, but also the linear input such as MASH is guaranteed, and the noise is avoided. The effect of 危-螖 modulator on phase noise of PLL is greatly reduced. The simulation results show that the 危-螖 modulator designed in this paper has excellent noise shaping characteristics. The output bottom noise is less than -200dB. Maximum output period sequence length 242.2) Quadrature multichannel ring oscillator with high power noise suppression ratio QVCO). The main characteristic of this QVCO is that the frequency is insensitive to the change of power supply in a certain range. LDO or other power management techniques can be used to improve the power noise resistance of VCO. The results of simulation show that the minimum sensitivity of normalized power supply is -46dB.VCO using the tuning of voltage-controlled resistor. Means. The output frequency tuning range of the designed VCO is 440 MHz to 5.18 GHz. The phase noise at 5GHz is -93dBc / Hz @ 1MHz 路3) high speed TSPC 4/5 dual-mode predivider with a pseudo-#number1# frequency divider structure. The delay on the critical path is reduced and the maximum working frequency is greatly increased. It can work in the range of 5. 5GHz. The maximum operating frequency is 40. 4 higher than that of the traditional structure in the same process. The double charge pump loop structure of RGC technology. The adjustable common-gate technology greatly improves the dynamic range of charge pump output. The current mismatch within 0.2-1.6V control voltage is less than 0.6. The dual charge pump structure is used in the PLL loop. Compared with the traditional single charge pump structure, the locking time is greatly reduced. In this paper, a charge pump phase-locked loop with wide band fractional N frequency division is designed using SMIC 0.18 m CMOS process. The output frequency ranges from 1.5 GHz to 4.5 GHz, and the step is about 12 KHz. The circuit simulation shows that the output frequency of CPPLL is 4.5 GHz. The phase noise is -94.36dBc / Hz @ 1MHz, and the maximum current consumption is 25.8mA at 1.8 V supply voltage. The output locking time of PLL is less than 8 us. the designed PLL has some advantages in the output frequency range and locking time in the same type of PLL.
【学位授予单位】：深圳大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.8;TN761

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