HART通信控制器的研究与设计

发布时间：2018-02-10 09:01

本文关键词： HART FSK 分组排序调制解调低功耗相位连续　出处：《沈阳工业大学》2017年硕士论文　论文类型：学位论文

【摘要】：HART协议是可寻址远程变送器数据通道协议的简称,是美国Rosement公司于1985年推出的一种用于现场智能仪表和控制室设备之间双向通信的协议规程。HART协议物理层使用FSK(频移键控)调制解调技术,在4mA-20mA模拟信号上叠加一个幅度为0.5mA均值为0的数字信号,以1200Hz和2200Hz交流信号分别代替数字信号的“1”和“0”,使模拟通信和数字通信同时进行且互不干扰。HART协议属于模拟系统向数字系统转变过程中的过渡产品,因此在当前的过渡时期具有较强的市场竞争能力,得到了较快的发展。本论文介绍了一种基于国外工艺设计的HART协议芯片,设计通过采用逆向分析的方法,结合HART协议标准。首先通过使用Chip Logic网表提取器对版图照片进行认清器件和数字逻辑门,并且把各个器件和逻辑门根据线网连接起来。然后根据芯片使用说明书对各个功能模块电路图进行整理,在整理数字电路时,从门级到RTL级的深层次分析是尤其困难的,而且费时费力,本论文提出了一种分组排序的数字电路深层次分析方法,大大缩短了分析时间。最后选用国内工艺根据所学理论知识并结合说明书对电路进行工艺移植,并利用相关软件对功能模块进行仿真验证,对于一些不满足原设计要求的模块将进行再设计。各个模块通过仿真验证之后,将各个模块连接起来再整体仿真验证。通过前期电路提取和后期功能模块整理以及对功能模块进行分析,整个HART协议芯片总共分为调制电路,解调电路,公共电路三个部分。这三个部分是整个电路的关键部分,所以对于这三个功能模块进行着重分析。在对整个电路进行分析之后,采用国内HHNECGE 0.35μm工艺对整个电路进行工艺移植。利用Hspice、Modelsim、ADMS模数混合仿真等仿真工具,分别对调制电路,解调电路以及整个电路进行各种测试以及模数混合仿真分析,通过仿真可以看出结果符合HART协议标准,各个功能模块工作正常,功耗大约为260μA。最后进行版图评估,面积大约为4000μm×4000μm,评估的面积只作为最终设计的面积参考。
[Abstract]:The HART protocol is the abbreviation of the addressable remote transmitter data channel protocol. In 1985, Rosement Company of the United States introduced a protocol protocol for two-way communication between intelligent instruments and control room devices. Hart protocol physical layer uses FSK-modulation and demodulation technology. A digital signal with an amplitude of 0.5 Ma is superimposed on the 4mA-20mA analog signal, The "1" and "0" of digital signals are replaced by 1200Hz and 2200Hz AC signals, respectively, so that analog communication and digital communication are simultaneously carried out and the .Hart protocol is a transitional product in the process of the transition from analog system to digital system. Therefore, in the current transition period, it has strong market competition ability and has been developed rapidly. This paper introduces a kind of HART protocol chip based on foreign process design, which is designed by reverse analysis. Combining with the standard of HART protocol. Firstly, by using Chip Logic net table extractor to recognize the device and digital logic gate of layout photo, Then the circuit diagram of each function module is arranged according to the instruction of the chip. When the digital circuit is arranged, the deep level analysis from gate level to RTL level is especially difficult. And it is time-consuming and laborious. In this paper, a method of deep level analysis of digital circuits is proposed, which greatly shortens the analysis time. Finally, the domestic technology is selected to transplant the circuit according to the theoretical knowledge and the instructions. And the functional modules are simulated and verified by relevant software. Some modules that do not meet the original design requirements will be redesigned. The whole HART protocol chip is divided into modulation circuit, demodulation circuit, and the whole HART protocol chip is divided into modulation circuit, demodulation circuit, and the whole HART protocol chip is divided into modulation circuit, demodulation circuit, and the whole HART protocol chip is divided into modulation circuit and demodulation circuit. Three parts of the common circuit. These three parts are the key parts of the whole circuit, so the three functional modules are analyzed emphatically. After the analysis of the whole circuit, The whole circuit is transplanted with HHNECGE 0.35 渭 m process in our country. The modulating circuit, demodulation circuit and the whole circuit are tested and analyzed respectively by using the HspiceMacksimsima ADMS mixed simulation tools, such as modulating circuit, demodulation circuit and the whole circuit. The simulation results show that the results conform to the standard of HART protocol, each functional module works normally, and the power consumption is about 260 渭 A. finally, the layout is evaluated, the area is about 4000 渭 m 脳 4000 渭 m, and the area evaluated is only used as the reference area of the final design.
【学位授予单位】：沈阳工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN915.05

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