基于uCGui图形界面的触控式可编程高阶调制信号发生器

发布时间：2018-03-05 17:04

本文选题：FPGA　切入点：AD9957　出处：《南京信息工程大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着现代卫星通信盲均衡技术的发展,盲均衡系统已进入产业化的阶段,为了测试盲均衡系统搭建一个完整的电子测量系统显得十分必要。卫星通信盲均衡技术的完整电子测量系统由信号源、模拟信道、盲均衡接收机组成,本文负责前端矢量信号源的设计。市场上高端的矢量调制信号发生器成本高昂、可携带性差,而低端的矢量调制信号发生器又存在调制功能单一、精度低、频率带宽低等缺点。本文针对这些问题设计了一款专用性高低成本的矢量信号源,主要工作如下:1)对比分析了传统的调制信号产生方案不足,本文采用FPGA+数字正交上变频芯片AD9957的调制信号产生方案,基带产生模块由FPGA内部数字逻辑搭建,AD9957对信号进行最高200MHz的正交上变频处理。2)使用7寸电容屏实现人机友好操作界面,FPGA内建一个Nios软核系统,为操作系统和图形库建立嵌入式平台,基于Avalon总线设计基带控制IP,基于时序规则设计显示控制IP,实现系统的高度可移植。3)对FPGA进行时序收敛设计,约束AD9957并行输出时序,结果表示FPGA基带产生模块最高工作频率是100MHz,进行了 IQ链路匹配分析,保证系统稳定有序工作。4) FPGA内基带产生模块设计了可变参数脉冲成型滤波器、单边带希尔伯特滤波器,实现了 2/4/8/16ASK调制、4/16/64/256QAM调制、DPSK调制、FSK/MSK 调制。5)对高阶调制信号发生器进行了软件设计,基于Nios SBT for Eclipse搭建了 uC/OSII操作系统和移植了 uC/GUI图形界面,设计了主控制界面。6)搭建系统测试平台,测试结果表明,本文设计的高阶调制信号发生器能够正确的产生各类调制信号,达到了预期的设计目标。
[Abstract]:With the development of modern satellite communication blind equalization technology, blind equalization system has entered the stage of industrialization. In order to test the blind equalization system, it is necessary to set up a complete electronic measurement system. The complete electronic measurement system of satellite communication blind equalization technology consists of signal source, analog channel and blind equalization receiver. This paper is responsible for the design of the front end vector signal generator. The high-end vector modulation signal generator in the market has high cost and poor portability, while the low end vector modulation signal generator has single modulation function and low precision. Aiming at these problems, this paper designs a vector signal source with high or low cost. The main work is as follows: (1) comparing and analyzing the shortage of traditional modulation signal generation scheme. In this paper, the modulation signal generation scheme of FPGA digital quadrature up-conversion chip AD9957 is adopted. The baseband generation module is built by FPGA internal digital logic to process the signal with up to 200MHz quadrature up-conversion. 2) using a 7-inch capacitive screen to realize the man-machine friendly operation interface and build a Nios soft core system. The embedded platform for the operating system and graphics library is established. The baseband control IPs are designed based on Avalon bus and the display IPs are designed based on the timing rules. The highly portable. 3) timing convergence design of the system is realized, and the parallel output timing of AD9957 is constrained. The results show that the maximum working frequency of the FPGA baseband generation module is 100 MHz. The IQ link matching analysis is carried out to ensure the stable and orderly operation of the system. 4) the variable parameter pulse shaping filter and the single sideband Hilbert filter are designed for the FPGA internal baseband generation module. 2 / 4 / 8 / 16 ASK modulation 4 / 16 / 64 / 256 QAM modulation / DPSK modulation / FSKR / MSK modulation .5) High order modulation signal generator was designed. Based on Nios SBT for Eclipse, the uC/OSII operating system was built and the uC/GUI graphic interface was transplanted. The test results show that the high-order modulation signal generator designed in this paper can produce all kinds of modulation signals correctly and achieve the desired design goal.
【学位授予单位】：南京信息工程大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN927.2

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