多路基于TLK2711高速串行图像数据的传输系统

发布时间：2018-03-08 15:06

本文选题：高速串行图像数据　切入点：IO利用率　出处：《液晶与显示》2017年10期 　论文类型：期刊论文

【摘要】：为提高多路高速串行图像数据传输在航天应用中的FPGA IO利用率,同时克服接收到的多路并行恢复数据相对相位不确定性问题,采用时钟分路器同时为多路TLK2711和FPGA提供低抖动时钟。对于串行数据发送,采用FPGA内部的数字时钟管理单元(DCM)对发送数据的相位进行调整,并采用TLK2711的内部环回功能进行发送数据和时钟相位的动态自适应调整。对于串行数据接收,采用高速异步数据缓存将多路相对相位不确定的数据调理为参考相同时钟,最终转换为满足Camera Link接口协议的图像数据。实验结果表明,采用时钟分路器可大大降低时钟抖动,该传输系统工作稳定可靠,最大传输速率可达6.8Gbit/s。此方法可大大提高FPGA内部的资源利用率,实现多路并行恢复数据的相对确定相位,满足多通道基于TLK2711的高速串行数据的高稳定传输要求。
[Abstract]:In order to improve the utilization ratio of FPGA IO for multichannel high-speed serial image data transmission in spaceflight applications, and to overcome the relative phase uncertainty of received multi-channel parallel recovery data, The clock splitter is used to provide low jitter clock for both TLK2711 and FPGA simultaneously. For serial data transmission, the digital clock management unit within FPGA is used to adjust the phase of the transmitted data. The internal loop function of TLK2711 is used to adjust the data and clock phase dynamically and adaptively. For serial data receiving, the multi-channel data with uncertain relative phase is adjusted to the same reference clock by high-speed asynchronous data cache. The experimental results show that the clock shunt can greatly reduce the clock jitter, and the system works stably and reliably. The maximum transmission rate is up to 6.8 Gbit / s. This method can greatly improve the internal resource utilization of FPGA, realize the relative determination of phase of multi-channel parallel data recovery, and meet the requirements of high stable transmission of multi-channel high-speed serial data based on TLK2711.
【作者单位】：中国科学院长春光学精密机械与物理研究所;
【基金】：国家自然科学基金(No.61405191) 吉林省科技发展计划项目(No.20160101273JC,No.20150520102JH)~~
【分类号】：TN919.8

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