HEVC帧内预测和变换模块的VLSI设计

发布时间：2018-03-13 07:06

本文选题：HEVC　切入点：帧内预测　出处：《合肥工业大学》2017年硕士论文　论文类型：学位论文

【摘要】：新一代视频编解码HEVC/H.265是ITU-T的视频编码专家组和ISO/IEC的动态图像专家组联合提出最新视频编码标准。与H.264相比,HEVC码流虽然减少50%,但是编解码端复杂度大大增加。本文首先研究HEVC帧内预测和变换模块的算法,然后结合硬件设计特点,对算法进行优化,最后根据优化后的算法进行VLSI设计。本文主要工作如下:1、HEVC帧内预测模块硬件电路设计针对帧内预测硬件架构电路面积较大、工作频率较低等问题,对三种预测模式(DC预测、Planar预测以及角度预测)分别开展优化设计。首先对帧内预测算法进行优化,然后使用模块复用以及寄存器缓存等技术对DC预测模式硬件电路进行优化;采用模块复用以及状态机跳转等方法对Planar预测模式硬件电路进行优化;使用查找表以及专用乘法器模块等技术对角度预测模式硬件电路进行优化。实验结果表明,与优化前相比,DC预测模式硬件电路在频率上提升40%,在逻辑门上减少32.4%,在处理延时上减少50%; Planar预测模式在工作频率上提升62%,在电路面积上减少51%,在处理延时上减少25%;角度预测模式电路在硬件效率上提升176%。2、HEVC变换模块硬件电路设计针对变换模块中DST算法硬件设计中存在的频率较慢、电路面积较大的问题,设计优化DST硬件电路。首先结合DST矩阵系数运算数值特点,提出一种改进的DST算法;在此基础上,本文设计对应于该算法专用乘法器,并通过转置缓存器以及流水线等方法,对电路的性能进行提升。由实验可得,与优化前相比,本文设计电路在电路面积上减少25.07%,在功耗上节省33.36%。
[Abstract]:The new generation video coding and decoding HEVC/H.265 is the latest video coding standard proposed by ITU-T video coding expert group and ISO/IEC dynamic image expert group. Compared with H. 264, the video stream is reduced by 50%, but the complexity of encoding and decoding end is greatly increased. Firstly, the algorithm of intra prediction and transform module in HEVC is studied. Then according to the characteristics of hardware design, the algorithm is optimized, and finally the VLSI is designed according to the optimized algorithm. The main work of this paper is as follows: 1. In order to solve the problem of low working frequency, three kinds of prediction modes, such as DC prediction, Planar prediction and angle prediction, are optimized. First of all, the intra prediction algorithm is optimized. Then the hardware circuit of DC prediction mode is optimized by module reuse and register buffer, and the hardware circuit of Planar prediction mode is optimized by module reuse and state machine jump. The hardware circuit of angle prediction mode is optimized by using lookup table and special multiplier module. The experimental results show that, Compared with before optimization, the hardware circuit of DC predictive mode is 40% higher in frequency, 32.4 in logic gate and 50 in processing delay; Planar prediction mode increases 62% in working frequency, 51th less in circuit area, and 51% in processing delay. The hardware circuit design of the DST transform module based on the angle prediction mode circuit improves the hardware efficiency of 1760.2HEVC transform module. The frequency in the hardware design of the DST algorithm in the transform module is relatively slow. In order to solve the problem of large circuit area, the DST hardware circuit is designed and optimized. Firstly, an improved DST algorithm is proposed according to the numerical characteristics of DST matrix coefficient operation, and then a special multiplier corresponding to this algorithm is designed in this paper. By means of transposing buffer and pipeline, the performance of the circuit is improved. The experimental results show that the circuit designed in this paper reduces the area of the circuit by 25.07 and saves 33.36 in power consumption.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN919.81

【参考文献】