基于概率计算的LDPC译码器设计与实现

发布时间：2018-03-13 15:28

本文选题：LDPC码　切入点：概率计算　出处：《电子科技大学》2017年硕士论文　论文类型：学位论文

【摘要】：LDPC码是一种重要的线性分组码,具有逼近香农限的特性,已广泛应用于深空通信、卫星通信、无线局域网中,并且成为下一代无线通信系统信道编码候选方案之一。由于缺乏低代价高性能的译码算法,LDPC码在提出的早期一直未能得到重视。随着迭代译码算法的提出与发展成熟,提出的BP、LLR BP和Min-Sum等LDPC译码算法的复杂度有所降低,但其译码器的实现复杂度依旧较高。在传统的数值表征和计算方法不能再有效地降低LDPC译码器实现复杂度的情况下,概率LDPC译码器被提出。通过采用新型的数值表征和计算方法,可以有效降低LDPC译码器的硬件实现复杂度。但是,现有概率计算译码方式下的变量节点(VN)依旧存在数据锁存等问题,将会严重制约概率计算的性能;同时,现有概率LDPC译码算法的性能较传统译码算法会略有损失。因此,概率LDPC译码器的应用实现方面还有很多的问题亟待研究和解决。本文以概率LDPC译码器的节点设计实现、性能提升策略为主要研究内容,重点研究了采用包编码技术的概率LDPC译码算法。首先介绍了概率计算的基本原理,并给出基于线性有限状态机利用概率比特序列实现逻辑运算单元的结构和仿真分析;然后回顾了 LDPC码原理以及其译码算法的改进过程,介绍了概率LDPC译码算法,详细描述了解决变量节点锁存问题的EM、TFM、MTFM重随机模块结构,给出了整个译码算法框架,并提出了改进译码性能的双路更新EM措施;而后在前期研究基础上,首次将包编码技术应用于概率LDPC译码器设计当中;最后设计了概率LDPC译码器的实现架构,采用VHDL编写了实现四种码率译码器的RTL代码,并进行了性能仿真验证。本文的主要工作和创新点如下:(1)针对变量节点锁存问题,提出了双路变量节点和校验节点更新EM的方式,使概率LDPC译码算法性能较传统更新EM的方式有所提升;(2)首次将包编码技术应用于概率LDPC译码器设计当中,显著提升了译码性能,同时保留了译码时延小、复杂度低的优势;(3)在MATLAB软件平台上进行了性能仿真验证及误比特率和误块率分析;采用Simulink和Modelsim协同仿真进行了概率LDPC译码器RTL代码的功能测试和性能分析。
[Abstract]:LDPC code is an important linear block code with the characteristic of approaching Shannon limit. It has been widely used in deep space communication, satellite communication and wireless local area network (WLAN). It has become one of the candidate schemes for channel coding in the next generation wireless communication system. Due to the lack of low cost and high performance decoding algorithm, LDPC codes have not been paid much attention in the early stage. With the development and development of iterative decoding algorithms, The complexity of the proposed LDPC decoding algorithms such as BP LLRBP and Min-Sum is reduced, but the implementation complexity of the decoder is still high. When the traditional numerical representation and computation methods can no longer effectively reduce the implementation complexity of the LDPC decoder, Probabilistic LDPC decoder is proposed. By using a new numerical representation and calculation method, the hardware implementation complexity of LDPC decoder can be reduced effectively. However, The existing probabilistic LDPC decoding methods still have some problems such as data latch, which will seriously restrict the performance of probabilistic computation, and the performance of the existing probabilistic LDPC decoding algorithm will be slightly reduced compared with the traditional decoding algorithm. Therefore, the performance of the existing probabilistic LDPC decoding algorithm will be slightly lower than that of the traditional decoding algorithm. There are still many problems to be solved in the application of probabilistic LDPC decoder. In this paper, the node design and implementation of probabilistic LDPC decoder and the performance enhancement strategy are the main research contents. The probabilistic LDPC decoding algorithm using packet coding technique is mainly studied. Firstly, the basic principle of probability calculation is introduced, and the structure and simulation analysis of logic operation unit based on linear finite state machine using probabilistic bit sequence are given. Then, the principle of LDPC code and the improvement process of its decoding algorithm are reviewed. The probabilistic LDPC decoding algorithm is introduced. The structure of EMN TFMM-MTFM heavy random module is described in detail, and the whole decoding algorithm framework is given. A dual-channel updating EM method to improve decoding performance is proposed, and then packet coding technology is applied to the design of probabilistic LDPC decoder for the first time on the basis of previous research. Finally, the implementation framework of probabilistic LDPC decoder is designed. The RTL codes of four rate decoders are compiled with VHDL, and the performance simulation is carried out. The main work and innovation of this paper are as follows: 1) aiming at the problem of variable node latching, a method of updating EM between two variable nodes and check node is proposed. The performance of probabilistic LDPC decoding algorithm is better than that of traditional updating EM.) the packet coding technique is applied to the design of probabilistic LDPC decoder for the first time, which improves the decoding performance significantly and preserves the decoding delay. The performance simulation and bit error rate and block error rate analysis are carried out on MATLAB software platform, and the function test and performance analysis of probabilistic LDPC decoder RTL code are carried out by Simulink and Modelsim co-simulation.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22

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