RSA中大素数生成算法优化及电路实现

发布时间：2018-03-18 19:08

本文选题：RSA算法　切入点：大素数生成　出处：《华中科技大学学报(自然科学版)》2017年06期 　论文类型：期刊论文

【摘要】：为了减少大素数生成时间并加快RSA(Rivest,ShamirAdleman)公钥密码算法的加解密速度,并行化实现了小素数试除和Miller-Rabin素性测试两大关键步骤,使其在进行素性测试的同时能进行小素数试除,从而大幅减少了小素数试除单独运算消耗的时间.为了加速Miller-Rabin素性测试须要反复调用的模乘运算单元,采用一种基于字的高基Montgomery算法及多级流水结构,设计了一种可配置的高速模乘运算电路.经FPGA(现场可编程门阵列)测试,在100 MHz频率下,生成的512bit大素数的平均耗时约为75ms,生成的1 024bit密钥对的平均耗时约为166ms,耗时只有参照结果的54.2%左右.
[Abstract]:In order to reduce the generation time of large prime numbers and speed up the encryption and decryption speed of RSA-Rivestor Shamiri Adlemann public key cryptosystem, two key steps, small prime number test and Miller-Rabin prime test, are realized by parallelization, so that the small prime number test can be carried out simultaneously. In order to speed up the Miller-Rabin prime test, the modular multiplication unit that needs to be repeatedly called is adopted a word-based high base Montgomery algorithm and multistage income structure. A configurable high speed modular multiplication circuit is designed, which is tested by FPGA (Field Programmable Gate Array) at 100 MHz frequency. The average time of 512bit large primes and 1,024bit key pairs is about 75msand 166msrespectively, which is only about 54.2% of the reference result.
【作者单位】：华中科技大学光学与电子信息学院;武汉工程大学电气信息学院;
【基金】：国家自然科学基金资助项目(61006020) 科技部科技型中小企业技术创新基金资助项目(14C26214422753) 湖北省重大科技项目(2015ACA063) 中央高校基本科研业务费专项资金资助项目(2014TS041)
【分类号】：TN918.4

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