极化码性能研究及其SCL译码算法的FPGA实现

发布时间：2018-03-19 09:03

  本文选题：信道极化　切入点：极化码　出处：《南京航空航天大学》2017年硕士论文　论文类型：学位论文

【摘要】：自从A.E Shannon提出Shannon定理以来,探寻能够达到Shannon极限的信道编码一直是通信领域的研究热点。近几十年来,两大接近Shannon极限的信道编码Turbo码和LDPC码日趋成熟,并已在现代通信中得到了广泛应用。随着土耳其教授Ardal Arikan基于信道极化现象提出极化码,极化码的研究脚步一刻也没有停止过。极化码有着线性的编码和译码复杂度和优越的性能,所以对于极化码的研究极具现实意义。本文旨在基于信道极化现象对极化码的性质以及编译码方法进行深入研究,并给出了一种基于FPGA的SCL译码器设计,主要的研究内容和创新点如下:(1)研究了Turbo码和LDPC码的基本编译码原理,并与极化码的基本编译码方法进行了宏观比较,说明各自的优缺点。通过对BEC和BSC等特定信道的组合和拆分,研究了信道极化现象的产生及性质,且不失一般性,可运用于AWGN信道等通信系统中的常见信道。(2)研究了极化码是如何基于极化现象产生的,在此基础上产生了极化码生成矩阵的迭代方法。重点对极化码SC、SCL、CA-SCL、BP等译码算法进行研究,通过仿真分析不同条件下的译码性能。信道挑选是极化码理论中极为重要的分支,本文在对现有经典信道挑选方法进行总结的同时提出一种AWGN信道下的新方法。该方法根据AWGN信道特性将其转化为BSC信道,再由BSC信道的巴式参数完成信道挑选。仿真表明,该方法在高信噪比情况下优于传统方法。(3)研究了适合硬件实现的最小和算法,并针对不同的量化宽度使用最小和算法进行性能仿真,最终对LLR进行8比特量化处理,而路径度量值采用12比特量化。总结了SC译码器硬件结构的演进发展过程,在此基础上为了减少系统资源的消耗,基于半并行结构提出了一种单计算单元的译码结构,并运用于本文的SCL译码器硬件设计中。详细介绍了本设计中各个子模块的功能,并使用Verilog语言在EDA工具QuartusⅡ上编写模块,然后调用Modelsim对程序进行了RTL级仿真。在系统时钟频率为300MHz的情况下,译码器的吞吐率可达6.24Mbps,资源利用率仅为6%。
[Abstract]:Since A.E Shannon put forward the Shannon theorem, it has been a hot topic in the field of communication to explore the channel coding that can reach the Shannon limit. In recent decades, two channel codes, Turbo code and LDPC code, which are close to the Shannon limit, have become more and more mature. And has been widely used in modern communication. With the introduction of polarization codes based on channel polarization phenomenon by Ardal Arikan in Turkey, The study of polarimetric codes has not stopped for a moment. Polarization codes have linear coding and decoding complexity and superior performance. Therefore, the study of polarization codes is of great practical significance. Based on the polarization phenomenon of the channel, the properties and encoding and decoding methods of polarization codes are studied in this paper, and a design of SCL decoder based on FPGA is presented. The main research contents and innovations are as follows: (1) the basic encoding and decoding principles of Turbo and LDPC codes are studied and compared with the basic encoding and decoding methods of polarimetric codes. By combining and splitting specific channels such as BEC and BSC, the generation and properties of channel polarization are studied, and the characteristics of polarization are studied without loss of generality. In this paper, we study how polarization codes are generated based on polarization phenomena, and then produce iterative method of polarization code generation matrix. The channel selection is an important branch of polarization code theory. In this paper, we summarize the existing classical channel selection methods and propose a new method under AWGN channel, which is converted to BSC channel according to the characteristics of AWGN channel, and then selected by the parameters of BSC channel. The simulation results show that, In the case of high SNR, this method is superior to the traditional method. It studies the minimum sum algorithm suitable for hardware implementation, and simulates the performance of the minimum sum algorithm for different quantization widths. Finally, the LLR is processed with 8-bit quantization. In order to reduce the consumption of system resources, a decoding structure of single computing unit is proposed based on the semi-parallel structure in order to reduce the consumption of system resources, and the evolution of the hardware structure of SC decoder is summarized. It is used in the hardware design of SCL decoder in this paper. The function of each sub-module in this design is introduced in detail, and the module is written on the EDA tool Quartus 鈪，

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