高速CMOS电荷泵锁相环设计

发布时间：2018-03-25 22:18

本文选题：电荷泵锁相环　切入点：CMOS技术　出处：《合肥工业大学》2017年硕士论文

【摘要】：随着集成电路设计和CMOS工艺的快速发展,集成电路已经进入系统级芯片(System on Chip,SoC)设计阶段。锁相环(Phase Locked Loop,PLL)作为片上系统中的时钟源,广泛应用在各类SoC芯片当中,是现代无线通信中的重要组成部分,其性能决定了整个系统性能的优劣。本文重点研究高速CMOS电荷泵锁相环的设计与实现问题,围绕电荷泵锁相环的理论基础、数学模型、电路设计、前端后端仿真、生产测试进行深入的研究。基于TSMC 0.18 μm 1P6M混合信号工艺,本文设计了一种具有快速锁定时间、较宽频率调节范围、低相噪的电荷泵锁相环。采用Top to Down的设计方法,完成对电路的系统设计到CMOS电路设计的流程。对电路中的死区、电流失配、稳定性、无法正常起振等非理想问题进行理论分析,并对电路进行优化,在电路设计时消除其影响。使用Cadence的Spectre对电路进行仿真,电路整体具有在输入参考频率23 MHz至600 MHz之间产生1.9 GHz至2.6 GHz的时钟信号功能。在中心频率2.3 GHz偏移载波频率10MHz的情况下,敏感单元环形压控振荡器的相位噪声为-112.9 dBc/Hz。本文对电路版图进行优化设计,分开布置数字模块和模拟模块,对模拟模块中最敏感的压控振荡器进行对称性设计和降噪处理。完成版图验证,并提交给代工厂进行流片,完成芯片测试电路设计,进行流片芯片的测试分析。测试分析表明,锁相环芯片可以正常工作,基本满足设计要求。本论文完成了高速CMOS电荷泵锁相环设计的全部过程,完成了整个芯片设计、测试流程。所设计的锁相环芯片可应用于微处理器中的时钟同步电路、无线通信收发器中的频率综合器、光纤通信中的时钟恢复电路以及多样相位采样电路等。
[Abstract]:With the rapid development of integrated circuit design and CMOS technology, integrated circuit has entered the stage of system-level chip system on ChipSoC. As a clock source in on-chip system, PLL is widely used in all kinds of SoC chips. As an important part of modern wireless communication, its performance determines the performance of the whole system. This paper focuses on the design and implementation of high speed CMOS charge pump phase-locked loop, which revolves around the theoretical basis and mathematical model of the charge pump phase-locked loop. Based on TSMC 0.18 渭 m 1P6M mixed signal technology, this paper designs a kind of fast locking time, wide frequency adjustment range, the design of the circuit design, the front-end simulation, the production test to carry on the thorough research, based on the TSMC 0.18 渭 m 1P6M mixed signal technology, Low phase noise charge pump phase-locked loop. Using Top to Down design method, complete the circuit system design to CMOS circuit design process. For the dead zone, current mismatch, stability, The non-ideal problems such as normal vibration are analyzed theoretically, and the circuit is optimized to eliminate its influence in circuit design. The Spectre of Cadence is used to simulate the circuit. The circuit as a whole has a clock signal function of 1.9 GHz to 2.6 GHz between the input reference frequencies of 23 MHz and 600 MHz.; in the case of the center frequency 2.3 GHz offset carrier frequency 10MHz, The phase noise of the sensitive unit ring voltage-controlled oscillator is -112.9 dBc / Hz. in this paper, the layout of the circuit is optimized and the digital module and the analog module are arranged separately. The symmetry design and noise reduction of the most sensitive VCO in the analog module are carried out. The layout verification is completed, and the layout verification is completed, and the chip test circuit is designed to complete the chip test circuit design. The PLL chip can work normally and basically meet the design requirements. In this paper, the design process of high speed CMOS charge pump PLL is completed, and the whole chip design is completed. The designed PLL chip can be used in clock synchronization circuit in microprocessor, frequency synthesizer in wireless communication transceiver, clock recovery circuit in optical fiber communication and various phase sampling circuit.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.8

【参考文献】