极化码串行抵消列表译码算法研究与FPGA实现

发布时间：2018-03-29 05:03

本文选题：极化码　切入点：译码算法　出处：《山东科技大学》2017年硕士论文

【摘要】：现代社会中随着数字通信技术的飞速发展,人们对数字通信系统的可靠性要求不断提高,对高速数据传输的需求也越来越大。信道编码是提升通信系统可靠性的有效方法,几十年来,编码学家一直在寻找可达香农界的信道编码方法。Arikan提出的极化码是第一种能够被严格证明达到信道容量的信道编码方法,是信道编码领域的重大突破。极化码有较低的编译码复杂度,在未来数字通信系统中的应用前景非常广阔。本文对极化码的串行抵消列表译码算法及其硬件实现进行了具体的研究,主要工作如下:(1)深入研究和改进极化码的译码算法。详细分析串行抵消(SC)译码算法的理论知识和译码特点,进一步研究了串行抵消列表(SCL)译码算法和多种增强的SCL译码算法,包括CA-SCL译码算法、aCA-SCL译码算法和PCA-SCL译码算法。设计跃进式译码算法,降低译码延时。设计了自适应的分段循环冗余校验辅助的SCL(aPCA-SCL)译码算法,仿真结果表明,aPCA-SCL译码算法相比aCA-SCL译码算法,在信噪比小于2dB时可降低11%-42%的平均搜索宽度。(2)对aPCA-SCL译码算法进行硬件实现。首先调整算法以适合硬件实现,设计合理的aPCA-SCL译码器硬件架构。然后给出一种资源使用少、性能损失较小的量化方案,其中信道LLR位宽为4,中间值LLR位宽为6,PM值位宽为8。相比浮点性能曲线,性能损失小于O.1dB。最后详细的介绍各模块的硬件设计,采用折叠式部分和结构并加以改进以适应跃进式译码算法,优化排序网络使速度提升35.43%,采用“Lazy Copy”技术降低路径复制导致的大量资源浪费。(3)完成aPCA-SCL译码器的功能仿真,并将aPCA-SCL译码器与极化码测试链路、上位机结合,搭建了完整的测试系统,完成FPGA验证和性能评估。验证结果表明,在码长N = 1024,码率R = 1/2,分段数P = 2,最大搜索宽度Lmax=4时,FPGA最高频率为212.27 MHz,最高吞吐率可达114.22 Mbps。与PCA-SCL译码器相比,在误帧率低于0.01时,吞吐率提升27.56%以上。
[Abstract]:With the rapid development of digital communication technology in modern society, the demand for reliability of digital communication system is increasing, and the demand for high-speed data transmission is also increasing. Channel coding is an effective method to improve the reliability of communication system. For decades, encoders have been looking for a Shannon bound channel coding method. Arikan's polarimetric code is the first channel coding method that can be strictly proven to reach channel capacity. Polarimetric code is a great breakthrough in the field of channel coding. The application prospect in the future digital communication system is very broad. In this paper, the serial cancellation list decoding algorithm of polarization code and its hardware implementation are studied in detail. The main work is as follows: (1) the decoding algorithm of polarization code is studied and improved in depth. The theoretical knowledge and decoding characteristics of serial cancellation decoding algorithm are analyzed in detail, and the serial canceling list decoding algorithm and several enhanced SCL decoding algorithms are further studied. The algorithm includes CA-SCL decoding algorithm and PCA-SCL decoding algorithm. The algorithm of leap forward decoding is designed to reduce the decoding delay. An adaptive algorithm for decoding SCLLA PCA-SCL, which is assisted by piecewise cyclic redundancy check, is designed. The simulation results show that compared with the aCA-SCL decoding algorithm, the PCA-SCL decoding algorithm can reduce the average search width of 11% -42% when the SNR is less than 2dB. A reasonable hardware architecture of aPCA-SCL decoder is designed. Then a quantization scheme with less resource usage and less performance loss is presented, in which the channel LLR bit width is 4, the intermediate value LLR bit width is 6 渭 m bit width is 8. Compared with the floating point performance curve, The performance loss is less than 0.1 dB. Finally, the hardware design of each module is introduced in detail, and the folding partial sum structure is adopted and improved to adapt to the leap forward decoding algorithm. The optimized sorting network increases the speed by 35.43 steps, and uses "Lazy Copy" technology to reduce the waste of a lot of resources caused by path replication) to complete the functional simulation of aPCA-SCL decoder, and combine the aPCA-SCL decoder with the polarization code test link, and the host computer. A complete test system is built to complete FPGA verification and performance evaluation. The verification results show that, When the code length N = 1024, the code rate R = 1 / 2, the number of segments P = 2, the maximum search width Lmax= 4, the maximum frequency of FPGA is 212.27 MHz, and the maximum throughput can reach 114.22 Mbps.Compared with the PCA-SCL decoder, the throughput is increased by more than 27.56% when the frame error rate is less than 0.01.
【学位授予单位】：山东科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22

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