应用于PCI-Express 2.0的双通道锁相环的研究与设计

发布时间：2018-04-09 07:02

本文选题：高速串行接口　切入点：锁相环　出处：《华侨大学》2017年硕士论文

【摘要】：高速串行接口具有连接简单、速度快、硬件开销小等特点,逐渐取代了传统并行接口。高速串行接口电路包含发送端和接收端,其中发送端的串化及接收端的解串均需要锁相环电路。本论文研究并设计了一种应用于PCI-Express 2.0的高速锁相环芯片。本论文从锁相环原理、噪声、电路及版图几个方面出发,对高速锁相环进行了深入研究,主要成果如下:(1)通过调研最前沿锁相环结构,针对低电源电压导致的调频范围小压控振荡器增益大的问题,提出了一种适用于PCI-Express2.0的粗调和细调相结合的高速单输入双通道结构的锁相环,其中粗调环路保证了大的频率覆盖范围,细调环路减小了压控振荡器增益。同时,为节约芯片量产成本,振荡器采用环形结构取代了传统电感电容结构,保证性能的前提下减小了面积和功耗。(2)深入分析了锁相环基本原理及各模块的噪声贡献,并基于Verilog-A语言进行了行为级建模,验证了滤波器参数、带宽、相位裕度、电荷泵电流、压控振荡器增益及分频比之间的折中关系,对具体电路设计时环路参数的选取具有一定指导意义。(3)采用参考时钟与反馈时钟相互采样的方式,设计了一种新型锁定检测电路,减小面积和功耗的同时可有效防止误锁定。(4)该芯片兼容了PCI-Express 2.0的高速和低速模式,其输出频率可在2.50GHz和1.25GHz两个频率点自由切换而不影响环路稳定性。同时为了满足测试需求,高速和低速模式下分别设计了可编程实现的多种环路带宽。(5)完成了整体芯片的电路设计,并根据混合信号版图布局布线规则对锁相环进行了版图设计、寄生参数提取及后仿验证。采用SMIC 55nm 1P8M CMOS工艺进行了电路及版图设计,芯片核心面积仅为0.152mm2,加入测试及IO后的总面积为1.495mm2。前仿结果表明,压控振荡器在1MHz频偏处的相位噪声分别为-98.2dBc/Hz@2.50GHz和-99.3dBc/Hz@1.25GHz;提取寄生参数后的仿真结果表明,锁相环锁定在2.50GHz和1.25GHz时,控制电压上的最大抖动分别为0.33mV和0.12mV。芯片核心电路采用2.5V和1.2V供电,2.50GHz时的最大功耗为15.6mW,1.25GHz时的最大功耗为9.6mW。
[Abstract]:High-speed serial interface has the advantages of simple connection, high speed and low hardware cost, so it has gradually replaced the traditional parallel interface.The high-speed serial interface circuit consists of the transmitter and receiver, in which both the serialization of the transmitter and the de-string of the receiver need phase-locked loop circuit.In this paper, a high-speed PLL chip for PCI-Express 2.0 is studied and designed.Based on the principle of phase-locked loop, noise, circuit and layout, this paper makes a deep research on high speed phase-locked loop. The main results are as follows: 1) by investigating the structure of the most advanced phase-locked loop,Aiming at the problem of large gain of small voltage controlled oscillator in frequency modulation range caused by low power supply voltage, a phase locked loop with high speed single input dual channel structure suitable for PCI-Express2.0 with coarse harmonic and fine modulation is proposed.The coarse tuning loop ensures a wide frequency coverage and the fine tuning loop reduces the gain of the VCO.At the same time, in order to save the production cost of the chip, the oscillator adopts a ring structure instead of the traditional inductor capacitor structure, which reduces the area and power consumption while ensuring the performance.) the basic principle of the PLL and the noise contribution of each module are deeply analyzed.The behavior level model based on Verilog-A language is used to verify the compromise between filter parameters, bandwidth, phase margin, charge pump current, VCO gain and frequency divider ratio.In this paper, a new type of lock detection circuit is designed by sampling the reference clock and the feedback clock in order to select the loop parameters in the specific circuit design.This chip is compatible with the high speed and low speed modes of PCI-Express 2.0, and its output frequency can be switched freely at the 2.50GHz and 1.25GHz frequency points without affecting the loop stability.At the same time, in order to meet the test demand, the circuit design of the whole chip is completed in high speed mode and low speed mode respectively, and the PLL is designed according to the layout and wiring rules of mixed signal layout.Parasitic parameter extraction and post-simulation validation.The circuit and layout are designed by using SMIC 55nm 1P8M CMOS technology. The core area of the chip is only 0.152 mm ~ 2, and the total area after adding test and IO is 1.495mm ~ 2.The maximum power consumption of the core circuit is 9.6mW at 2.5V and 1.2V power supply 2.50GHz when the maximum power consumption is 15.6mWN 1.25GHz.
【学位授予单位】：华侨大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.8

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