二进制和非二进制LDPC译码器的FPGA设计与实现

发布时间：2018-04-28 05:55

本文选题：LDPC + 译码器　；参考：《西南交通大学》2017年硕士论文

【摘要】：自从信息论的创始人香农(Shannon)在其论文中提出了信道编码的理念后,学者们就开始投身于研究发现复杂度低、易于实现且逼近香浓极限的性能优异的信道编码。上个世纪六十年代,麻省理工学院的Robert Gallager第一次提出了 LDPC码,即低密度奇偶校验码(Low Density Parity Check Codes)。但是由于当时的计算能力有限,LDPC一直没有引起人们的注意,直到1996年,人们才重新发现了 LDPC码的优异性能。这些年来,FPGA技术的进步越来越快,并且FPGA具有功能性能强大,开发周期很短,可以重复进行编程等特点,已成为硬件设计中的首选器件之一。因此,本文采用FPGA来设计和实现一种可以合理的兼顾吞吐量、资源和复杂度的LDPC码编译码器。本文将基于二进制LDPC和非二进制LDPC编译码器的FPGA设计和实现展开研究:首先,基于对现有的二进制LDPC码和非二进制LDPC码译码算法的研究和分析,确定了以硬件实现复杂度较低且性能损失较少的Min-Sum算法和EMS算法分别作为二进制LDPC译码器和非二进制LDPC译码器FPGA实现的译码算法并使用Matlab进行误码率仿真。其次,本文确定了部分并行结构作为本文译码器的实现结构,使用硬件描述语言Verilog以及VHDL进行各模块实现。另外,为了提高译码器的实用性,本文对译码器的结构进行了优化使其可以灵活配置以支持不同码率或者码长的LDPC码译码;为了提高连续译码能力,程序增加了数据乒乓操作输入数据存储功能;为了提高吞吐率,译码器没有固定译码迭代次数,并且加入了可以设置的最大迭代次数,如果在最大迭代次数内完成译码,则迭代停止。最后,本文使用Modelsim 6.5C作为仿真工具对编译码器进行功能仿真测试,并使用Xilinx ISE 14.6软件对译码器进行综合及布局布线,目标芯片为:Xilinx XC6VSX315T。对综合结果进行分析,本文实现的二进制和非二进制LDPC编译码器都具有较高的吞吐率并且复杂度较低,能够合理的兼顾吞吐量、资源和复杂度。
[Abstract]:Since Shannon, the founder of information theory, put forward the idea of channel coding in his thesis, scholars have begun to devote themselves to the research of channel coding with low complexity, easy to implement and close to the limit of fragrance. In the 1960s, Robert Gallager of the Massachusetts Institute of Technology first proposed LDPC codes, which are called low Density Parity Check codes. However, due to the limited computing power at that time, the excellent performance of LDPC codes was not discovered until 1996. In recent years, the progress of FPGA technology is more and more rapid, and FPGA has the characteristics of powerful function, short development period, and can be repeated programming, which has become one of the first choice devices in hardware design. Therefore, FPGA is used to design and implement a LDPC codec which can reasonably balance throughput, resource and complexity. In this paper, the design and implementation of FPGA based on binary LDPC and non-binary LDPC decoders are studied. Firstly, based on the research and analysis of the existing decoding algorithms of binary LDPC codes and non-binary LDPC codes, The Min-Sum algorithm and the EMS algorithm, which have lower hardware complexity and less performance loss, are chosen as the decoding algorithms of binary LDPC decoder and non-binary LDPC decoder FPGA, respectively, and the BER simulation is carried out with Matlab. Secondly, this paper determines part of the parallel structure as the implementation structure of the decoder, using the hardware description language Verilog and VHDL to implement each module. In addition, in order to improve the practicability of the decoder, the structure of the decoder is optimized so that it can be configured flexibly to support the decoding of LDPC codes with different bit rates or code lengths, and to improve the ability of continuous decoding. The program adds data ping-pong operation input data storage function; in order to improve throughput, the decoder does not have fixed decoding iterations, and adds the maximum number of iterations that can be set, if the decoding is completed within the maximum number of iterations, Then the iteration stops. Finally, this paper uses Modelsim 6.5C as the simulation tool to carry on the function simulation test to the codec, and uses the Xilinx ISE 14.6 software to carry on the synthesis and the layout wiring to the decoder, the target chip is: Xilinx XC6VSX315T. The results show that both binary and non-binary LDPC encoders have high throughput and low complexity, and can reasonably take into account throughput, resource and complexity.
【学位授予单位】：西南交通大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22;TN791

【参考文献】