HEVC关键模块并行算法的设计与基于GPU的实现

发布时间：2018-05-03 03:37

本文选题：HEVC + 帧间预测　；参考：《大连理工大学》2016年硕士论文

【摘要】：近年来随着高清和超高清视频的发展,视频应用的多样性和高分辨率给以往的视频编码标准带来了极大的挑战。为了能够满足视频应用的需求,2013年国际电信联盟(ITU-T)的视频编码专家组和国际标准化组织(ISO/IEC)的移动视频专家组通力合作,发布了最新一代的视频编码标准——HEVC。相对于H.264/AVC,在相同图像质量的前提下,平均可以减少50%的码率。HEVC在获得出色视频压缩性能的同时其超高的计算复杂度制约了HEVC的广泛应用。为此有必要提高HEVC的编码效率。GPU大量的运算单元非常适合通用并行计算。NVIDIA公司于2007年推出的全新通用并行计算架构(CUDA)采用类C语言为实现大规模可并行的数据任务提供了良好的计算平台。利用GPU的众核特性并行实现视频编码算法已经成为加速视频编码的有效解决方式。本文重点针对HEVC帧间预测和环路滤波的关键模块进行并行算法的设计,并在CUDA平台上编程实现。针对分像素插值,本文设计了一种高效的分像素插值并行算法；针对运动估计环节,本文分别设计了基于梯状并行的整像素和分像素运动搜索算法；针对DCT变换和IDCT变换,本文设计了一种基于蝶形运算的多层级并行算法；针对量化和反量化模块进行并行算法的设计；本文设计了一种全并行的去方块滤波算法；针对样点自适应补偿模块,对边界补偿和边带补偿分别设计了像素分类和信息统计、补偿值求取的并行算法,设计了基于对角结构的参数融合并行算法,设计了全并行的滤波补偿算法。本文在CPU+GPU异构平台上用CUDA语言编程实现了所有设计的并行算法。实验结果表明,对于1080P的高清视频序列,在保证图像重构质量的前提下,与原始串行算法相比,本文设计的并行算法能够取得20倍以上的加速比,能够有效提高帧间回路的编码效率。
[Abstract]:In recent years, with the development of high-definition and ultra-high-definition video, the diversity and high resolution of video applications have brought great challenges to the previous video coding standards. In order to meet the needs of video applications, the Video coding expert Group of the International Telecommunication Union (ITU) in 2013 and the Mobile Video expert Group of ISO / IEC of the International Organization for Standardization (ISO / IEC) jointly issued the latest generation of video coding standard, HEVC. Compared with H.264 / AVC, with the same image quality, the average bit rate can be reduced by 50%. HEVC can achieve excellent video compression performance and its high computational complexity restricts the wide application of HEVC. Therefore, it is necessary to improve the coding efficiency of HEVC. GPU with a large number of computing units is very suitable for general parallel computing. NVIDIA introduced a new universal parallel computing architecture in 2007. It provides a good computing platform. Parallel implementation of video coding algorithm based on GPU's multikernel characteristics has become an effective solution to accelerate video coding. This paper focuses on the design of parallel algorithms for the key modules of inter-frame prediction and loop filtering in HEVC, and implements them on the CUDA platform. For sub-pixel interpolation, this paper designs an efficient sub-pixel interpolation parallel algorithm; for motion estimation, this paper designs the whole pixel and sub-pixel motion search algorithm based on ladder parallel; for DCT transform and IDCT transform, In this paper, we design a multi-level parallel algorithm based on butterfly operation; design a parallel algorithm for quantization and inverse quantization module; design a fully parallel de-block filter algorithm; For boundary compensation and sideband compensation, the parallel algorithms of pixel classification and information statistics, compensation value calculation, parameter fusion parallel algorithm based on diagonal structure and full-parallel filtering compensation algorithm are designed respectively. In this paper, all the parallel algorithms are implemented on CPU GPU heterogeneous platform with CUDA programming language. The experimental results show that the parallel algorithm designed in this paper can achieve a speedup ratio of more than 20 times compared with the original serial algorithm under the premise of guaranteeing the image reconstruction quality for 1080P high-definition video sequences. It can effectively improve the coding efficiency of the inter-frame loop.
【学位授予单位】：大连理工大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN919.81

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