新一代外贸155测速雷达中频数字接收机的研究与实现

发布时间：2018-05-12 03:42

本文选题：中频数字接收机 + 数字下变频　；参考：《南京理工大学》2017年硕士论文

【摘要】：现代大多数雷达接收机系统均应用了数字化技术,雷达数字接收机的发展得益于数字技术的完善。本文重点对雷达中频接收机的数字处理作了一定的研究。当前雷达设备日新月异,因此研发雷达中频数字接收机系统对我国雷达设备的更新换代而言有十分重要的战略意义。本文结合新一代外贸155测速雷达系统的实际需求,设计了一套基于FPGA的雷达中频数字接收机。中频数字接收的理论基础涉及到信号的带通采样,数字下变频,多采样率数字信号抽取。滤波器算法的重要理论有最大误差最小化准则、交替定理和交错点组定理。接收机实现的硬件平台有中频放大器,A/D变换器件,FPGA芯片等。我遵循模块化的设计思路,通过模拟预处理和模数转换硬件电路、FPGA内部数字信号处理和逻辑控制,实现了测速雷达中频数字接取机的设计。在FPGA内部数字信号处理中,基于数字正交下变频和分布式算法理论,提出一种多相滤波结构的数字下变频方法,完成信号频谱搬移;基于级联抽取和切比雪夫逼近理论,提出积分梳妆滤波器和半带滤波器级联抽取的方法,降低了基带信号速率。结合FPGA硬件平台和VerilogHDL软件编程,完成了对雷达系统前端中频回波信号的实时接收。测试结果验证了本设计的正确性和可行性。
[Abstract]:Most modern radar receiver systems use digital technology, and the development of radar digital receiver benefits from the improvement of digital technology. This paper focuses on the digital processing of radar if receiver. At present, radar equipment is changing with each passing day, so the research and development of radar if digital receiver system is of great strategic significance to the upgrading of radar equipment in China. According to the actual demand of the new generation of foreign trade 155-speed radar system, a set of radar if digital receiver based on FPGA is designed in this paper. The theoretical basis of if digital reception involves band-pass sampling, digital downconversion and multi-sampling rate digital signal decimation. The most important theories of filter algorithm include maximum error minimization criterion, alternating theorem and staggered point group theorem. The hardware platform of the receiver includes if amplifier / A / D converter and FPGA chip. I follow the modular design idea, through analog preprocessing and analog to digital conversion hardware circuit FPGA internal digital signal processing and logic control, to achieve the speed measurement radar if digital receiver design. In FPGA internal digital signal processing, based on the theory of digital quadrature downconversion and distributed algorithm, a digital down-conversion method with multi-phase filter structure is proposed to complete the signal spectrum shift, based on cascaded decimation and Chebyshev approximation theory. An integrated dressing filter and a half band filter are proposed to reduce the baseband signal rate. Combined with FPGA hardware platform and VerilogHDL software, the real time receiving of if echo signal in front end of radar system is completed. The test results verify the correctness and feasibility of the design.
【学位授予单位】：南京理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN957.5

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