应用于可外同步DC-DC变换器的锁相环的设计

发布时间：2018-05-14 20:40

  本文选题：DC-DC变换器 + 可外同步　； 参考：《西南交通大学》2017年硕士论文

【摘要】：随着电子系统的发展和进步,应用需求增多促使互联网,物联网和信息安全密码系统大力发展。各种不同功能的芯片被集成在一个系统中,其对电源要求各不相同,为了减少相互之间的影响,增加系统的稳定性,就要求电源芯片能够有更强的兼容性。本文针对以上问题,利用了锁相环技术来外同步DC-DC变换器的时钟频率,并且设计实现一种应用于可外同步DC-DC变换器的电荷泵锁相环电路。首先介绍了本文研究的背景和意义,指出了电源管理芯片市场情况和发展趋势。介绍了电源管理芯片中DC-DC变换器的开关频率对其性能的影响,并且给出了利用锁相环技术的可外同步变换器的优势。同时还介绍了锁相环电路的结构和相关指标,分析了两类锁相环的动态特性。然后分别给出了本文电荷泵锁相环的具体实现电路,对电荷泵电路进行了优化设计,加入基准源保证了电荷泵的充电和放电电流的稳定性,并且基准源还能为后续的电路提供偏置电流和比较的基准阈值电压。设计了具体的压控振荡器电路,其增益可以随着外同步频率而改变,减小了系统的锁定时间。并且其控制电压被限定在指定范围内。最后本文基于TSMC 0.18um CMOS的工艺模型,利用Candence软件进行了具体电路图的绘制并且利用Hspice软件对各个子电路和整体电路进行了仿真验证。仿真结果表明,在3V的电源电压供电情况下,本文的电荷泵锁相可以在TT,SS,FF三个工艺角下和-20℃到120℃温度范围内同步频率为500KHz到2MHz的外部时钟,锁定时间最大为68us最小为27us,功耗小于223.8uW。并且系统能够在压控振荡器的控制电压在0.68V到1.14V之外时屏蔽外部时钟。电路的指标都满足预期,在DC-DC变换器等应用中有很高的实用价值。
[Abstract]:With the development and progress of electronic system, the Internet of things, Internet of things and information security cryptosystem are greatly developed. In order to reduce the influence of each other and increase the stability of the system, the power chip is required to be more compatible. In order to solve the above problems, this paper uses phase-locked loop (PLL) technology to synchronize the clock frequency of DC-DC converter, and designs and implements a charge pump phase-locked loop (CPPLL) circuit which can be applied to extrinsic synchronous DC-DC converter. Firstly, the background and significance of this paper are introduced, and the market situation and development trend of power management chip are pointed out. The influence of switching frequency on the performance of DC-DC converter in power management chip is introduced, and the advantage of external synchronous converter using PLL technology is given. At the same time, the structure and related indexes of PLL circuit are introduced, and the dynamic characteristics of two kinds of PLL circuits are analyzed. Then, the realization circuit of the charge pump phase-locked loop is given respectively, and the charge pump circuit is optimized and the stability of charge and discharge current is ensured by adding the reference source. The reference source can also provide bias current and reference threshold voltage for subsequent circuits. A specific VCO circuit is designed. The gain can be changed with the external synchronization frequency and the locking time of the system is reduced. And its control voltage is limited to a specified range. Finally, based on the process model of TSMC 0.18um CMOS, the specific circuit diagram is drawn by using Candence software, and each sub-circuit and the whole circuit are simulated and verified by Hspice software. The simulation results show that the external clock of 500KHz to 2MHz can be synchronized with the phase locked phase of the charge pump in the three process angles and the temperature range from -20 鈩，

本文编号：1889386