一种消除反馈延迟的全数字锁相环

发布时间：2019-04-29 08:17

【摘要】：针对传统数字锁相环存在的反馈滞后造成系统动、静态性能退化的问题,提出一种消除反馈滞后一拍的方法,以无反馈滞后理想数字锁相环为参考模型,利用数字锁相环当前输出与上一时刻输出,计算得到与理想数字锁相环一致的结果,从而消除反馈滞后一拍。所提出的锁相环仅以两个乘法器的额外开销即可大幅增强锁相环的稳定性,并且使在s域内设计的性能指标能够在z域内严格实现,克服了传统数字锁相环性能退化的问题。仿真和实验结果表明,所提改进的数字锁相环阶跃响应和频率特性均与理想数字锁相环一致,显著提高了锁相环性能,所提新算法增加的计算量较少,具有较大的实际应用价值。
[Abstract]:In order to solve the problem of dynamic and static performance degradation caused by feedback delay in traditional digital phase locked loop, a method to eliminate feedback lag and one beat is proposed, and the ideal digital phase locked loop without feedback lag is used as reference model. By using the current output and the last time output of the digital phase-locked loop, the results are consistent with those of the ideal digital phase-locked loop, thus eliminating the feedback lag by one beat. The proposed PLL can greatly enhance the stability of PLL with the additional overhead of only two multipliers, and the performance index designed in s domain can be implemented strictly in z domain, which overcomes the problem of performance degradation of traditional digital PLL. Simulation and experimental results show that the step response and frequency characteristics of the proposed digital phase-locked loop are consistent with those of the ideal digital phase-locked loop, and the performance of the proposed digital phase-locked loop is significantly improved, and the computational complexity of the proposed new algorithm is less than that of the improved digital phase-locked loop. It has great practical application value.
【作者单位】：北京交通大学电气工程学院;
【基金】：国家自然科学基金(51407005) 高等学校博士学科点专项科研基金(20130009120032) 中央高校基本科研业务费(2016JBM056)资助项目
【分类号】：TN911.8

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