规则LDPC码在GPU上的加速译码
发布时间：2019-05-17 18:58
【摘要】：针对图形处理器高速并行的特点和规则低密度奇偶校验码译码过程中的可并行部分,提出了使用图形处理器来加速规则低密度奇偶校验码译码的方法.该方法在图形处理器上采用以节点的边并行代替节点并行进行译码,提高了线程利用率;同时,在译码过程中采用图形处理器高速的片上内存——共享内存和寄存器来存储数据,使数据存储减少对全局内存的依赖,缩短数据访问时间.仿真结果显示,使用边并行和片上内存,译码速度约是图形处理器不使用文中优化方法的低密度奇偶校验码译码程序的5.32~10.41倍.
[Abstract]:According to the characteristics of high speed parallelism of graphics processor and the parallel part of the decoding process of regular low density parity check code, a method of using graphics processor to accelerate the decoding of regular low density parity check code is proposed. In this method, the edge parallel of the node is used instead of the node parallel decoding on the graphics processor, which improves the thread utilization. At the same time, in the decoding process, the graphics processor high-speed on-chip memory-shared memory and register are used to store the data, so that the data storage can reduce the dependence on global memory and shorten the data access time. The simulation results show that the decoding speed is about 5.32 鈮，
本文编号：2479333
[Abstract]:According to the characteristics of high speed parallelism of graphics processor and the parallel part of the decoding process of regular low density parity check code, a method of using graphics processor to accelerate the decoding of regular low density parity check code is proposed. In this method, the edge parallel of the node is used instead of the node parallel decoding on the graphics processor, which improves the thread utilization. At the same time, in the decoding process, the graphics processor high-speed on-chip memory-shared memory and register are used to store the data, so that the data storage can reduce the dependence on global memory and shorten the data access time. The simulation results show that the decoding speed is about 5.32 鈮，
本文编号：2479333
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