基于FPGA的BDPSK直接序列扩频通信系统的研究

发布时间：2019-06-02 12:07

【摘要】：直接序列扩频通信由于其出色抗干扰能力、频带利用率和保密性,近年来被广泛的应用到军事和民用领域。本论文设计的通信系统,采用大规模可编程逻辑器件(FPGA),所设计与实现的扩频通信系统的发射端、接收端,各模块,包括重要的载波发生器(NCO)、各种滤波器、及数字环路滤波器、锁相环等各模块,都集成在一个FPGA芯片上,提高了通信系统的稳定性与可靠性。本文研究了现有的扩频算法,完成了发送端、接收端各个模块的设计与调试,具体所做的工作如下:(1)结合FPGA的特点,对现有的扩频码同步方法进行了优化和改进,提出了一种便于FPGA器件实现的PN码同步方法,最终完成信号的解扩。抗白噪声能力可达-25.38 dB,抗单频噪声干扰能力可达-18.3dB。(2)在载波同步电路的设计中,对传统的Costas环结构进行了改进,经过试验测试,节省了资源提高了同步电路的可靠性。(3)在位同步电路的设计中。结合传统的加扣时钟位同步、Gardner位同步算法,提出了一种“基于跳变检测调整频率字”的位同步算法。该算法精度介于上述两者之间,结合了锁相环具有的良好跟踪、记忆性能,结构简单便于实现。是一种面向判决的位同步提取算法,更适用于FPGA器件的硬件电路实现。(4)通过RS232串口实现了计算机产生的基带信号源与FPGA开发板的调制及解调系统的数据通信接口设计,该接口设计可移植性好,便于对通信系统的性能进行测试。
[Abstract]:Direct sequence spread spectrum communication has been widely used in military and civil fields in recent years because of its excellent anti-interference ability, band efficiency and confidentiality. The communication system designed in this paper adopts the transmitter, receiver and modules of the spread spectrum communication system designed and implemented by large-scale programmable logic device (FPGA), including all kinds of filters of important carrier generator (NCO),. And digital loop filter, phase-locked loop and other modules are integrated on a FPGA chip, which improves the stability and reliability of the communication system. In this paper, the existing spread spectrum algorithms are studied, and the design and debugging of each module at the transmitter and receiver are completed. The specific work is as follows: (1) according to the characteristics of FPGA, the existing spread spectrum code synchronization methods are optimized and improved. In this paper, a PN code synchronization method is proposed, which is convenient for FPGA devices to realize, and finally the signal despreading is completed. The anti-white noise ability of-25.38 dB, is up to-18.3 dB. (2) in the design of carrier synchronization circuit, the traditional Costas ring structure is improved and tested. The resources are saved and the reliability of the synchronization circuit is improved. (3) in the design of the in-place synchronization circuit. Combined with the traditional clock synchronization and Gardner bit synchronization algorithm, a bit synchronization algorithm based on jump detection and frequency word adjustment is proposed. The accuracy of the algorithm is between the above two, which combines the good tracking and memory performance of the phase-locked loop, and the structure is simple and easy to implement. It is a bit synchronization extraction algorithm for decision, which is more suitable for the hardware circuit implementation of FPGA devices. (4) the data communication interface between the baseband signal source generated by computer and the modulation and demodulation system of FPGA development board is designed through RS232 serial port. The interface design has good portability and is convenient to test the performance of communication system.
【学位授予单位】：青岛大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN914.42

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