深度学习卷积神经网络VLIW加速器设计与实现

发布时间：2018-05-20 19:16

本文选题：卷积神经网络 + 并行计算　；参考：《苏州大学》2016年硕士论文

【摘要】：近年来,卷积神经网络(CNN)算法及其在视觉感知领域的应用很大程度上改变了传统的机器视觉框架。但因为CNN算法大量的计算工作负载使其很难在高实时性,嵌入式场合得以广泛应用。最近,有一些国际著名的学术、商业机构推出了其专用的解决方案,用来降低功耗并提高性能,但大量的数据传输与访问仍然是一个棘手的挑战。本文的主要的工作如下:1.整合并优化了CNN卷积层,进行了细粒度的算法并行性分析,提出了Intra Output Feature Map的并行思路;对片上片外存储模型进行分析并为CNN设置了较通用的存储解决方案;2.提出了一种全新的CNN硬件加速器结构,设定了指令集与工作模式,用户可以使用简单的VLIW指令实现多种参数的CNN网络层;3.构建了基于ZYNQ的SOC芯片设计验证平台框架,并对CNN加速器进行验证;4.使用28nm低功耗工艺库实现了CNN加速器ASIC,与其它先进的CNN加速器相比,在实现相近或更好的吞吐量情况下,本文的加速器降低了50%的外部存储访问量,能够在0.303mm2的芯片面积上达到102GOp/s@800MHz的吞吐量,最大功耗仅为68mW.
[Abstract]:In recent years, the convolutional neural network (CNN) algorithm and its applications in the field of visual perception have greatly changed the traditional machine vision framework. However, due to the large computational workload of CNN algorithm, it is difficult to be used in high real time, so it is widely used in embedded environment. Recently, some internationally renowned academic and commercial organizations have launched their own solutions to reduce power consumption and improve performance, but massive data transmission and access is still a tricky challenge. The main work of this paper is as follows: 1. This paper integrates and optimizes the CNN convolution layer, analyzes the parallelism of fine grained algorithm, puts forward the parallel thinking of Intra Output Feature Map, analyzes the on-chip and off-chip storage model and sets up a general storage solution for CNN. A new structure of CNN hardware accelerator is proposed. Instruction set and working mode are set up. User can use simple VLIW instruction to realize CNN network layer with multiple parameters. The framework of SOC chip design and verification platform based on ZYNQ is constructed, and the CNN accelerator is verified. The CNN accelerator is realized by using 28nm low-power process library. Compared with other advanced CNN accelerators, the accelerator in this paper reduces the external storage access by 50% compared with other advanced CNN accelerators in the case of similar or better throughput. It can achieve the throughput of 102GOp/s@800MHz on the chip area of 0.303mm2, and the maximum power consumption is only 68 MW.
【学位授予单位】：苏州大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TH824.4;TP183

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