高分辨率示波器数据采集与处理模块设计

发布时间：2018-04-02 03:26

本文选题：JESD204B　切入点：JESD204B　出处：《电子科技大学》2017年硕士论文

【摘要】：高分辨率示波器正逐渐成为电子测试仪器中一个非常重要的组成部分,它比普通示波器有着更高的测量精度,能够更好的观察信号的细节,有着更高的信噪比。JESD204B串行传输协议是近几年在模数转换器(ADC)中发展起来的协议,它比传统的并行传输有着巨大的优势,在高分辨率ADC中它的优势更加明显。时间交替采样ADC(TIADC)是常用的提高采样率的有效手段,但是在JESD204B这种新兴的串行传输协议下的时间交替采样系统却研究的很少,甚至国内还没有相关的报道。论文研究设计高分辨率示波器的数据采集与处理模块,主要研究内容如下:(1)研究JESD204B串行传输协议下的TIADC系统。深入剖析了JESD204B串行传输协议,分析了它比传统的并行传输的具有的优势,研究JESD204B协议构成稳定的TIADC系统的条件,从系统时钟、ADC和FPGA接收端研究如何实现JESD204B协议下的TIADC系统。(2)研究TIADC系统中的误差校正。分析TIADC系统中的误差模型,提出了数理统计和频谱分析的TIADC误差估计方法,在比较数字后校正的几种方案后在FPGA中高效的实现了用于校正时间误差的FIR滤波器。(3)研究高分辨率示波器中用于提高波形捕获率的三维映射模块。分析了并行架构的示波器系统,比较了高分辨率示波器与普通示波器三维映射模块的差异,实现了高分辨率示波器中的三维映射。试验和测试表明,本文实现了JESD204B串行传输协议下的TIADC系统,采样率达到了5GSPS,垂直分辨率为12位,经过对TIADC系统的偏置、增益和时间误差的校正使有效位数达到了8.85位。三维映射架构使得高分辨率示波器的波形捕获率达到80,000wfms/s。
[Abstract]:High-resolution oscilloscope is gradually becoming a very important part of electronic testing instrument. It has higher measuring precision than ordinary oscilloscope, and can observe the details of signal better.JESD204B serial transmission protocol with higher signal-to-noise ratio (SNR). JESD204B is a protocol developed in ADC in recent years. It has great advantages over traditional parallel transmission and is more obvious in high resolution ADC.Time alternating sampling (JESD204B) is an effective method to improve the sampling rate. However, there are few researches on the time alternating sampling system under JESD204B, which is a new serial transmission protocol, even there are no related reports in China.In this paper, the data acquisition and processing module of high resolution oscilloscope is designed. The main research contents are as follows: 1) the TIADC system under JESD204B serial transmission protocol is studied.This paper deeply analyzes the JESD204B serial transmission protocol, analyzes its advantages over the traditional parallel transmission, and studies the conditions under which the JESD204B protocol constitutes a stable TIADC system.The error correction in the TIADC system is studied from the system clock ADC and the FPGA receiver. How to realize the TIADC system under the JESD204B protocol.The error model of TIADC system is analyzed, and the TIADC error estimation method of mathematical statistics and spectrum analysis is proposed.After comparing several schemes of digital post-correction, the FIR filter for correcting time error is implemented efficiently in FPGA. The 3D mapping module used to improve waveform capture rate in high-resolution oscilloscopes is studied.This paper analyzes the oscilloscope system with parallel architecture, compares the 3D mapping module between high resolution oscilloscope and ordinary oscilloscope, and realizes the 3D mapping in high resolution oscilloscope.The experiments and tests show that the TIADC system based on JESD204B serial transmission protocol is implemented in this paper. The sampling rate is up to 5 GSPS and the vertical resolution is 12 bits. The effective bit number is 8.85 bits after bias, gain and time error correction of the TIADC system.Three-dimensional mapping architecture allows high-resolution oscilloscopes to achieve waveform capture rates of 800 wfms / s.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP274.2;TM935.3

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