基于PCI总线的串行通讯控制器的设计

发布时间：2018-05-10 04:55

本文选题：HDLC协议 + PCI总线　；参考：《东南大学》2016年硕士论文

【摘要】：随着互联网逐渐进入大数据时代,研究高效高速的串行通讯成为一种必然趋势。路由器的广域网接口卡一般都采用基于外围部件互联(Peripheral Component Interconnect, PCI)总线的高速串行通讯控制器进行控制。高级数据链路控制协议(High Level Data Link Control, HDLC)是数据链路层中最常用的协议,它具有强大的差错检测功能和高可靠、高效率、透明传输的特点,能应用于任何面向比特的高速数据传输系统中。因此,本文采用HDLC协议控制器处理串行通讯中的数据,保证了数据的正确传输。本文在分析PCI总线与]HDLC协议的基础上,设计了一种基于PCI总线的串行通讯控制器,描述了HDLC控制器与PCI总线进行通信的接口信号。设计分为发送和接收两个模块,两大模块的工作互不干扰,分别由各自的控制器加以控制。HDLC发送器包括并串移位寄存器、帧校验序列(Frame Check Sequence, FCS)发生器、零插入、标志停止字的产生以及发送控制等模块,HDLC接收器包括标志停止字检测、零检测、FCS校验器、串并转换、接收控制等模块。其中,FCS校验部分采用循环冗余校验(Cyclic Redundancy Check, CRC),以保证数据传输的正确性和完整性。通过对发送和接收控制模块的重点描述,说明了系统中数据发送和接收处理的详细过程。本文采用Verilog HDL语言进行电路设计,并且使用Modelsim软件进行功能仿真。在TSMC90nm工艺下,电路的工作频率可达到400MHz。最后,通过FPGA验证证明了设计能够正确完成数据的发送和接收功能。此外,若传输一字节数据,在使用16位CRC时发送模块的吞吐率最高可达80Mb/s,接收模块的吞吐率最高可达94Mb/s,能满足高速串行通讯的需求。
[Abstract]:With the Internet gradually entering big data era, the study of high-efficiency and high-speed serial communication has become an inevitable trend. The WAN interface card of the router is usually controlled by a high speed serial communication controller based on peripheral Component Interconnect (PCI) bus. High Level Data Link Control (HDLC) is the most commonly used protocol in the data link layer. It has powerful error detection function and features of high reliability, high efficiency and transparent transmission. It can be used in any bit-oriented high-speed data transmission system. Therefore, the HDLC protocol controller is used to deal with the data in serial communication to ensure the correct transmission of data. Based on the analysis of PCI bus and] HDLC protocol, a serial communication controller based on PCI bus is designed, and the interface signal between HDLC controller and PCI bus is described. The design is divided into two modules: sending and receiving. The work of the two modules is not interfered with each other. The transmitter is controlled by their respective controllers. The transmitter includes serial shift registers, frame Check Sequence, FCS) generator and zero insertion. The signal stop word generation and transmission control module HDLC receiver includes sign stop word detection, zero detection FCS calibrator, series-parallel conversion, receiving control and other modules. In order to ensure the correctness and integrity of data transmission, cyclic Redundancy check (CRCs) is adopted in the part of FCS verification. The detailed process of data sending and receiving in the system is explained by describing the module of sending and receiving control. In this paper, Verilog HDL language is used for circuit design, and Modelsim software is used for functional simulation. In TSMC90nm process, the working frequency of the circuit can reach 400 MHz. Finally, FPGA verification proves that the design can complete the function of sending and receiving data correctly. In addition, if one byte of data is transmitted, the throughput of transmission module can reach 80 MB / s when using 16-bit CRC, and the throughput of receiving module can reach 94 MB / s, which can meet the demand of high speed serial communication.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP273

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